Optical co-processor architecture using array of weak optical perceptron
AssigneeGeorgia Tech Research Corporation
InventorsYashar Kiarashinejad, Ali Adibi
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Abstract
An optical co-processor architecture using array of weak optical perceptron is disclosed in a computing architecture for a neuro-inspired computing platform. The use of weak optical perceptron in this architecture facilitates the manufacturability and use of an exemplary computing microchips having an array of weak-learners in which a plurality of weak-learners of the array are selectively grouped and their outputs are aggregated to provide a coprocessing output for a given computing and decision-making task in an integrated photonic system.
Claims20
An integrated artificial intelligence (AI) photonic chip comprising
- a processor;
- and
- a photonic co-processor, the photonic co-processor comprising a first interface to the processor and a photonic structure that couples to the first interface and configured with an array of optical perceptrons, wherein the array includes a plurality of optical perceptrons that are each configured as a weak learner having an output that is aggregated with other weak learner outputs of the array to perform an AI-related operation, wherein the aggregated output of the weak learners is reconfigurable and wherein a first weak learner having a first associated accuracy characteristic and a second weak learner having a second associated accuracy characteristic, the aggregated output has a third associated accuracy characteristic higher than the first associated accuracy characteristic and the second associated accuracy characteristic, the photonic structure comprising:
- an input structure configured as a waveguide for an electromagnetic (EM) input;
- a detection layer comprising an array of detection elements, each detection element of the array of detection elements has a pre-defined spatial region that is configured to generate a respective output for a given optical perceptron;
- and
- two or more reconfigurable layers of metasurface structures located between the input structure and the detection layer, including a first metasurface layer and a second metasurface layer, each of the first metasurface layer and the second metasurface layer being re-configurable, via first control signals from the processor to through the first interface to first controllable elements associated with the first metasurface layer and the second metasurface layer to form a first array of aggregated weak learners to vary transmission of the EM input to the detection layer, and via second control signals from the processor to through the first interface to second controllable elements associated with the first metasurface layer and second metasurface layer to form a second array of aggregated weak learners to vary transmission of the EM input to the detection layer.
Dependencies are inferred from the claim text.