Fractional frequency-divider circuit

A method, comprising:

• receiving, by a phase generation circuit, an input clock signal with a first frequency;
• generating, by the phase generation circuit, a plurality of phase signals using the input clock signal, wherein the plurality of phase signals are delayed from the input clock signal by corresponding delay times;
• combining, by a phase selection circuit, pairs of the plurality of phase signals to generate corresponding ones of a plurality of local clock signals;
• generating, by the phase selection circuit, a plurality of selection signals using the plurality of local clock signals;
• and
• selecting, by the phase selection circuit using the plurality of local clock signals, different phase signals of the plurality of phase signals at corresponding times to generate an output clock signal with a second frequency, wherein a first ratio of the first frequency to the second frequency is a non-integer value;
• and
• wherein generating the plurality of phase signals includes:
• generating, by a frequency divider circuit using the input clock signal, a different clock signal with a third frequency, wherein a second ratio of the first frequency to the third frequency is an integer value;
• and
• delaying, by a delay-locked loop circuit, the different clock signal by different delay values to generate corresponding ones of the plurality of phase signals.

An apparatus, comprising:

• a first device coupled to a communication bus;
• and
• a second device coupled to the communication bus, wherein the second device includes a transceiver circuit that includes a fractional frequency-divider circuit configured to:
• receive an input clock signal with a first frequency;
• generate a plurality of phase signals using the input clock signal, wherein the plurality of phase signals are delayed from the input clock signal by corresponding delay times;
• combine pairs of the plurality of phase signals to generate corresponding ones of a plurality of local clock signals;
• generate a plurality of selection signals using the plurality of local clock signals;
• and
• select, using the plurality of local clock signal, different phase signals of the plurality of phase signals at corresponding times to generate an output clock signal with a second frequency, wherein a first ratio of the first frequency to the second frequency is a non-integer value;
• and
• wherein the transceiver circuit is configured to transmit data to the first device using the output clock signal;
• and
• wherein the fractional frequency-divider circuit includes a delay-locked loop circuit, and wherein to generate the plurality of phase signals, the fractional frequency-divider circuit is further configured to:
• generate, using the input clock signal, a different clock signal with a third frequency, wherein a second ratio of the first frequency to the third frequency is an integer value;
• and
• delay, using the delay-locked loop circuit, the different clock signal by different delay values to generate corresponding ones of the plurality of phase signals.