Adaptive gate driver with negative temperature coefficient (NTC) resistor
AssigneeVertiv Corporation
InventorDilesh Arvind Raut
Life of this patent
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Abstract
An adaptive gate drive circuit for an insulated gate bridge transistor, IGBT, based semiconductor switch provides a gate resistance device for reducing timing delays and switching losses associated with an increase in switch junction temperature. The gate resistance device is disposed close to the switch junction and including a negative temperature coefficient, NTC, thermistor and linear gate resistor connected in parallel. When the thermistor senses an increase in the junction temperature of the semiconductor switch, gate resistance via the linear gate resistor is reduced to bring the junction temperature back to thermal equilibrium with minimal delay, allowing the semiconductor switch to switch faster and reducing associated switching losses.
Claims18
A gate drive circuit for a semiconductor device, comprising:
- at least one semiconductor switch configured to supply a power to the semiconductor device in response to a control signal received from a control switch, the at least one semiconductor switch associated with:
- a radiated emissions limit;
- and
- a junction temperature;
- wherein a gate drive voltage associated with the power is one of:
- a positive voltage corresponding to an on state, the on state associated with at least one of a turn-on switching timing or a turn-on switching loss;
- or
- a non-positive voltage corresponding to an off state, the off state associated with at least one of a turn-off switching timing or a turn-off switching loss;
- and
- a gate resistance device serially connected between the control switch and the at least one semiconductor switch, the gate resistance device thermally coupled to the at least one semiconductor switch, the gate resistance device comprising a negative temperature coefficient (NTC) thermistor and a gate resistor connected in parallel;
- wherein the gate resistance device is configured to:
- sense the junction temperature associated with at least one of the on state or the off state based on a relationship between the junction temperature and a resistance of the NTC thermistor;
- and
- in response to a change in the junction temperature, adjust one or more of the associated turn-on or turn-off switching timing or the associated turn-on or turn-off switching loss by adjusting a gate resistance of the gate resistor based on an inverse linear relationship between the junction temperature and a resistance of the gate resistance device.
A method for optimal switching of a semiconductor device, the method comprising:
- serially connecting a gate resistance device between a semiconductor switch of the semiconductor device and a control switch of the semiconductor device,
- the semiconductor switch configured for supplying a power to the semiconductor device in response to a control signal received from the control switch, the semiconductor switch associated with a radiated emissions limit and a junction temperature, a gate drive voltage associated with the power corresponding to at least one of an on state or an off state, the on state associated with a turn-on switching timing and a turn-on switching loss, the off state associated with a turn-off switching timing and a turn-off switching loss;
- and
- the gate resistance device thermally coupled to the semiconductor switch and comprising a negative temperature coefficient (NTC) thermistor and a gate resistor connected in parallel;
- sensing, via the NTC thermistor, the junction temperature associated with at least one of the on state or the off state based on a relationship between the junction temperature and a resistance of the NTC thermistor;
- and
- in response to a change in the junction temperature, adjusting one or more of the associated turn-on or turn-off switching timing or the associated turn-on or turn-off switching loss by adjusting a gate resistance of the gate resistor based on an inverse linear relationship between the junction temperature and a resistance of the gate resistance device.
Dependencies are inferred from the claim text.