Low power flip-flop and integrated circuit including the same

A flip-flop comprising:

• a slave latch;
• and
• a master latch configured to generate a first data signal and a second data signal based on a clock signal, a data input signal, and an inverted data input signal, and generate a latch signal based on the clock signal, an input of the slave latch, and the second data signal, wherein the first data signal is complementary to the inverted data input signal and the second data signal is complementary to the data input signal,
• wherein the slave latch is configured to latch the input of the slave latch based on the clock signal and the latch signal, and comprises:
• a first inverter configured to invert the input of the slave latch;
• and
• a second inverter configured to update the input of the slave latch based on an output of the first inverter, the latch signal and the clock signal.

A method of latching a data input signal based on a clock signal, the method comprising:

• based on the clock signal, the data input signal, and an inverted data input signal, generating a first data signal complementary to the inverted data input signal and a second data signal complementary to the data input signal;
• generating a latch signal based on the clock signal, an input of a slave latch, and the second data signal;
• and
• latching the input of the slave latch based on the clock signal and the latch signal,
• wherein the latching comprises inverting the input of the slave latch using a first inverter and updating the input of the slave latch, using a second inverter, based on an output of the first inverter, the latch signal and the clock signal.