Delay buffer unit and operating method thereof, computing device and operating method thereof

A computing device, comprising:

• a delay computing array, comprising 2M rows and N columns of delay buffer units, 2N word lines corresponding to the N columns, N bit lines corresponding to the N columns, and 2M source lines corresponding to the 2M rows,
• wherein N delay buffer units in each of the 2M rows are connected in series to form a row of delay chain, each two adjacent rows of delay chains constitute a delay processing combination, two rows of delay chains in each delay processing combination receive a same input signal;
• two delay buffer units located in a same column in each delay processing combination are respectively connected with two word lines corresponding to the same column;
• each of the delay buffer units comprises a first-stage inverter, a second-stage inverter and a delay adjustment sub-unit,
• an input terminal of the first-stage inverter serves as an input terminal of the delay buffer unit,
• an input terminal of the second-stage inverter is connected with an output terminal of the first-stage inverter, and an output terminal of the second-stage inverter serves as an output terminal of the delay buffer unit,
• the delay adjustment sub-unit is connected with a first terminal of the first-stage inverter, and is connected with a source line corresponding to a row where the delay adjustment sub-unit is located, a bit line corresponding to a column where the delay adjustment sub-unit is located, and a word line corresponding to the column where the delay adjustment sub-unit is located,
• the delay adjustment sub-unit comprises a memristor, and is configured to adjust a transmission delay of the first-stage inverter by controlling and using the memristor according to a first control signal provided by a corresponding word line.