Clock generator and method of clock generation

A clock generator comprising:

• a ring oscillator configured to generate an output frequency signal;
• a frequency detector configured to compare a frequency of the output frequency signal with r times a frequency of a reference frequency signal and to generate a feedback signal based on the comparison;
• and
• a control circuit configured to control a loop delay parameter of the ring oscillator and a supply voltage of the ring oscillator based on the feedback signal, wherein the control circuit is configured:
• to reduce the frequency of the output frequency signal when its frequency is higher than r times the frequency of the reference frequency signal by reducing the supply voltage without modifying the loop delay parameter, unless the supply voltage has reached a minimal level, in which case the loop delay parameter is then increased;
• and
• to increase the frequency of the output frequency signal when its frequency is lower than r times the frequency of the reference frequency signal by reducing the loop delay parameter without modifying the supply voltage, unless the loop delay parameter has reached a minimal level, in which case the supply voltage is then increased.