US 12,700,852 B1Granted

System and method for reducing circuit elements in high-performance flip-flops

OwnerSteve Daoinventor

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Abstract

A latch circuit comprising a tristate driver and a storage feedback loop and having minimal circuit elements is disclosed. The tristate driver and feedback loop couple to internal nodes of a separate latch circuit to reduce total circuit element count by collapsing elements with common functionality into a single circuit element. The latch circuit presents only one transistor gate load to a clock signal, and the output of the separate latch is coupled to the input of the latch circuit to form a flip-flop. The flip-flop generates an output signal based on a received input signal when the clock signal is at second level and stores the received input signal when the clock signal is at first level. The flip-flop is fully static, contention-free, with near-zero setup time, with less circuit elements than prior arts, and can be configured to integrate multi-input logic functions.

Claims20

Dependent claims

A flip-flop circuit comprising:

an input terminal for receiving a main input signal;
a clock terminal for receiving a clock signal;
an output terminal for sending an output signal;
and
an input propagation unit comprising:
a first clock-activated transistor as the first top-most transistor of a first stack structure;
a second clock-activated transistor as the second top-most transistor of a second stack structure;
a first top node;
a second top node;
a first bottom node;
a second bottom node;
a first keeper device;
a second keeper device;
a latch, wherein said latch having at most one clock-activated transistor and wherein said latch couples to either said first top node and said second top node, or said first bottom node and said second bottom node and wherein said latch is coupled to said first keeper device of said input propagation unit;
wherein said first keeper device is activated upon the discharging of said first top node to low power supply, wherein said second keeper device is activated upon the discharging of said second top node to said low power supply;
wherein said latch further comprises:
a tristate driver to receive a first input from an output of the input propagation unit and a second input from said clock signal;
a keeper sub-circuit to maintain said storage node at constant level when said clock signal is at first level;
and
an output buffer to isolate output signal from said storage node;
wherein said tristate driver writes said first input to a storage node when said clock signal is at second level;
wherein said tristate driver comprises a third clock-activated transistor configured as a pull-down network coupled to either said first bottom node or said second bottom node.

19 more elements

A flip-flop circuit comprising:

an input terminal for receiving a main input signal;
a clock terminal for receiving a clock signal;
an output terminal for sending an output signal;
and
an input propagation unit comprising:
a first clock-activated transistor as the first top-most transistor of a first stack structure;
a second clock-activated transistor as the second top-most transistor of a second stack structure;
a first top node;
a second top node;
a first bottom node;
a second bottom node;
a first keeper device;
a second keeper device;
a latch, wherein said latch having at most one clock-activated transistor and wherein said latch couples to either said first top node and said second top node, or said first bottom node and said second bottom node and wherein said latch is coupled to said first keeper device of said input propagation unit;
wherein said first keeper device is activated upon the discharging of said first top node to low power supply, wherein said second keeper device is activated upon the discharging of said second top node to said low power supply;
wherein said latch further comprises:
a tristate driver to receive a first input from an output of the input propagation unit and a second input from said clock signal;
a keeper sub-circuit to maintain said storage node at constant level when said clock signal is at first level;
and
an output buffer to isolate output signal from said storage node;
wherein said tristate driver writes said first input to a storage node when said clock signal is at second level;
wherein the keeper sub-circuit comprises a pull-up transistor coupled to either said first top node or second top node and wherein said keeper sub-circuit further comprises a pull-down transistor coupled to either said first bottom node or said second bottom node.

19 more elements

A flip-flop circuit comprising:

an input terminal for receiving a main input signal;
a clock terminal for receiving a clock signal;
an output terminal for sending an output signal;
and
an input propagation unit comprising:
a first clock-activated transistor as the first top-most transistor of a first stack structure;
a second clock-activated transistor as the second top-most transistor of a second stack structure;
a first top node;
a second top node;
a first bottom node;
a second bottom node;
a first keeper device;
a second keeper device;
a latch, wherein said latch having at most one clock-activated transistor and wherein said latch couples to either said first top node and said second top node, or said first bottom node and said second bottom node and wherein said latch is coupled to said first keeper device of said input propagation unit;
wherein said first keeper device is activated upon the discharging of said first top node to low power supply, wherein said second keeper device is activated upon the discharging of said second top node to said low power supply;
wherein said latch further comprises:
a tristate driver to receive a first input from an output of the input propagation unit and a second input from said clock signal;
a keeper sub-circuit to maintain said storage node at constant level when said clock signal is at first level;
and
an output buffer to isolate output signal from said storage node;
wherein said tristate driver writes said first input to a storage node when said clock signal is at second level;
wherein said output signal of said output buffer is either of same or opposite polarity to said main input signal.

19 more elements

Dependencies are inferred from the claim text.

Facts

Application: 18/780,510Filed 23 Jul 2024 · continuation
Priority: 8 May 2022
Granted: 4 Aug 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

H03K 3/012
Details: modifications of generator to improve response time or to decrease power consumption
H03K 3/356121
Using additional transistors in the input circuit: with synchronous operation
H03K 3/35625
Of the primary-secondary type: using complementary field-effect transistors
H03K
Pulse technique