Bidirectional counter and integrated circuit including the same
AssigneesSamsung Electronics Co., Ltd., Research & Business Foundation Sungkyunkwan University
InventorsJaeha Lee, Bai-Sun Kong, Bomin Joo
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Abstract
Disclosed are a bidirectional counter and a method of generating output data. The bidirectional counter may include at least one first flip-flop configured to generate, based on at least one first local clock, at least one first bit including a least significant bit (LSB) of the output data and a second bit that is an upper bit of the at least one first bit, and a local clock generation circuit configured to generate, in response to an up signal that is activated, the at least one first local clock based on the input clock and the at least one first bit, and to generate, in response to the up signal that is deactivated, the at least one first local clock based on the input clock and at least one inverted first bit.
Claims20
A bidirectional counter configured to generate output data based on an input clock, the bidirectional counter comprising:
- at least one first flip-flop configured to generate, based on at least one first local clock, at least one first bit of the output data and a second bit that is an upper bit of the at least one first bit, the at least one first bit including a least significant bit (LSB) of the output data;
- and
- a local clock generation circuit configured to generate, in response to an up signal that is activated, the at least one first local clock based on the input clock and the at least one first bit, and to generate, in response to the up signal that is deactivated, the at least one first local clock based on the input clock and at least one inverted first bit that corresponds to an inverted version of the at least one first bit.
A bidirectional counter configured to generate output data based on an input clock, the bidirectional counter comprising:
- at least one first flip-flop configured to generate, based on at least one first local clock, a most significant bit (MSB) of the output data and at least one first bit that is lower than the MSB;
- a first pre-evaluation circuit configured to generate, in response to an up signal that is activated, at least one first ripple carry based on the at least one first bit and a second bit that is lower than the at least one first bit, and to generate, in response to the up signal that is deactivated, the at least one first ripple carry based on an inverted second bit that corresponds to an inverted version of the second bit and at least one inverted first bit that corresponds to an inverted version of the at least one first bit;
- and
- a first local clock selection circuit configured to generate the at least one first local clock based on the input clock, a first carry input, and the at least one first ripple carry.
A method of generating output data that increases or decreases according to an input clock, the method being performed by a counter comprising a local clock generation circuit and at least one first flip-flop, the method comprising:
- receiving an up signal;
- generating, by the local clock generation circuit, in response to the up signal that is activated, at least one first local clock based on the input clock and at least one first bit of the output data, the at least one first bit including a least significant bit (LSB) of the output data;
- generating, by the local clock generation circuit, in response to the up signal that is deactivated, the at least one first local clock based on the input clock and at least one inverted first bit that corresponds to an inverted version of the at least one first bit;
- and
- generating, by the at least one first flip-flop, based on the at least one first local clock, the at least one first bit and a second bit that is an upper bit of the at least one first bit.
Dependencies are inferred from the claim text.