Pulse width modulation decoder circuit, corresponding device and methods of operation
AssigneeSTMicroelectronics S.r.l.
InventorsVanni Poletto, Ivan Floriani
Life of this patent
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Abstract
A circuit for decoding a pulse width modulated (PWM) signal generates an output signal switching between a first and second logic values as a function of a duty-cycle of the PWM signal. Current generating circuitry receives the PWM signal and injects a current to and sinks a current from an intermediate node as a function of the values of the PWM signal. A capacitor coupled to the intermediate node is alternatively charged and discharged by the injected and sunk currents, respectively, to generate a voltage. A comparator circuit coupled to the intermediate node compares the generated voltage to a comparison voltage and drives the logic values of the output signal as a function of the comparison.
Claims16
A method, comprising:
- receiving a control signal having a first control value indicative of a reset phase and a second control value indicative of a duty cycle evaluation phase;
- coupling an intermediate node to a data demodulation output node in response to the first control value of the control signal;
- decoupling the intermediate node from the data demodulation output node in response to the second control value of the control signal;
- and
- while the control signal has the second control value:
- injecting a current into the intermediate node as a function of a first value of an input pulse width modulated (PWM) signal in a PWM period and sinking a current from the intermediate node as a function of a second value of that input PWM signal in the same PWM period, thereby changing the voltage across the capacitor;
- comparing the changing voltage to a reference voltage;
- and
- driving the data demodulation output node to generate a data demodulation output signal having a first output value or to a second output value in response to a result of said comparing.
A method, comprising:
- receiving an input pulse width modulated (PWM) signal at an input node;
- generating a control signal having an alternating first control value and second control value;
- operating a first decoder circuit that receives the input PWM signal in a reset phase when the control signal has the first control value and in a duty-cycle evaluation phase when the control signal has the second control value;
- operating a second decoder circuit that receives the input PWM signal in the reset phase when the control signal has the second control value and in the duty-cycle evaluation phase when the control signal has the first control value;
- and
- propagating to an output node an output signal of the first decoder circuit when the control signal has the second control value and propagating to the output node an output signal of the second decoder circuit when the control signal has the first control value.
Dependencies are inferred from the claim text.