GPIO circuit and chip

A general-purpose input/output (GPIO) circuit, comprising at least one output driver branch each including output driver transistors, wherein:

• each output driver transistor comprises a drain coupled to a GPIO pin;
• and a gate coupled to a corresponding pre-driver circuit, wherein the pre-driver circuit comprises:
• a conventional pre-driver circuit, comprising an input terminal coupled to a signal to be output and an output terminal coupled to a gate of a corresponding output driver transistor;
• a pre-driver transistor, comprising a gate coupled to a slope control signal and a drain coupled to one terminal of the conventional pre-driver circuit;
• and
• a slow pre-driver (SPD) circuit, coupled between a source and the drain of the pre-driver transistor, wherein the SPD circuit comprises a reference current source and a current mirror coupled to the reference current source;
• wherein when the slope control signal is so configured that the pre-driver transistor is turned on, and the SPD circuit and the conventional pre-driver circuit are turned on, the output driver transistor is turned on in a normal mode;
• or
• wherein when the slope control signal is so configured that the pre-driver transistor is turned off, and the SPD circuit and the conventional pre-driver circuit are turned on, the output driver transistor is turned on in a slope-controlled mode, in which the output driver transistor is turned on more slowly than in the normal mode.