Phase interpolator layout
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei Shuo Lin, Wei Chih Chen
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Abstract
Circuits, devices, and methods relating to a phase interpolator are described herein. The phase interpolator may include a first plurality of functional units and a second plurality of functional units, and may be controlled, in part, by an encoding scheme. The phase interpolator may be designed to have a layout such that a turn-on resistance across the first plurality of functional units in response to a first code of the encoding scheme is equal to a turn-on resistance across the second plurality of functional units in response to a second code of the encoding scheme.
Claims20
A circuit comprising:
- a first multiplexer configured to output a first signal along a first path and a second multiplexer configured to output a second signal along a second path,
- wherein the first multiplexer and second multiplexer are each configured to receive a coarse tune signal for controlling a phase of the first signal and a phase of the second signal;
- a first plurality of functional units connected along the first path, wherein the first plurality of functional units is configured to take the first signal as input and output a first phase-shifted signal;
- and
- a second plurality of functional units connected along the second path, wherein the second plurality of functional units is configured to take the second signal as input and output a second phase-shifted signal,
- wherein the first plurality of functional units and the second plurality of functional units are configured to receive a fine tune signal that is configured to control a first number of functional units of the first plurality of functional units in an on-state and a second number of functional units of the second plurality of functional units in an on-state, and
- wherein the first path and the second path intersect such that the first phase-shifted signal and the second phase-shifted signal combine to form an interpolated signal comprising a phase between the phase of the first signal and the phase of the second signal.
An integrated circuit device comprising:
- a sampler configured to receive an input data signal;
- a digital filter configured to receive sampled signals from the sampler;
- a controller configured to generate control signals based on filtered signals received from the digital filter;
- and
- a phase interpolator configured to receive control signals from the controller and clock signals from a reference loop and output an interpolated signal,
- wherein the phase interpolator comprising an array of functional units, wherein the array of functional units is divided into a first half and a second half each comprising a same number of functional units, and
- wherein the phase interpolator is configured to balance a turn-on resistance across the functional units of the first half in response to a first fine tune code with a turn-on resistance across the functional units of the second half in response to a second fine tune code.
A method of generating an interpolated signal comprising:
- generating a first signal, by a first multiplexer, wherein the first signal has a phase based on a first coarse tune code applied to the first multiplexer;
- generating a second signal, by a second multiplexer, wherein the second signal has a phase based on a second coarse tune code applied to the second multiplexer;
- applying, by a first plurality of functional units, a first phase shift to the first signal to generate a first phase-shifted signal, wherein a magnitude of the first phase shift is determined by a fine tune code;
- applying, by a second plurality of functional units, a second phase shift to the second signal to generate a second phase-shifted signal, wherein a magnitude of the second phase shift is determined by the fine tune code;
- and
- generating the interpolated signal by combining the first phase-shifted signal and the second phase-shifted signal.
Dependencies are inferred from the claim text.