Display substrate having gate driving circuit and display device

A display device, comprising a display substrate, wherein the display substrate comprises:

• a base substrate;
• and
• a gate driving circuit provided on a peripheral region of the base substrate, wherein the gate driving circuit comprises a plurality of shift register circuits that are arranged in a first direction,
• each shift register circuit comprises an input circuit, a control circuit, an output circuit and an output noise reduction circuit,
• the input circuit is connected to an input terminal and configured to control a level of a first node in response to an input signal that is input by the input terminal,
• the control circuit is connected to the first node, a second node and a third node,
• the output circuit is connected to the third node and an output terminal, respectively, and is configured to provide an output signal to the output terminal,
• the output noise reduction circuit is connected to the second node and the output terminal, respectively, and is configured for noise reduction on the output terminal,
• the control circuit comprises a first transistor, a second transistor and a third transistor,
• a first electrode of the first transistor is directly connected to the second node and configured to control a level of the second node,
• a first electrode of the second transistor is connected to the third node, a second electrode of the second transistor is connected to a first voltage line to receive a first voltage, a gate electrode of the second transistor is directly connected to the first node, and the second transistor is configured to control a level of the third node in response to the level of the first node,
• a first electrode of the third transistor is connected to the third node and configured to control the level of the third node, and
• at least two selected from group consisting of an active layer of the first transistor, an active layer of the second transistor and an active layer of the third transistor extend in the first direction and are sequentially arranged in the first direction,
• wherein the control circuit further comprises:
• a fourth transistor and a fifth transistor,
• a first electrode of the fourth transistor is connected to the first voltage line to receive the first voltage, a second electrode of the fourth transistor is connected to the second node, a gate electrode of the fourth transistor is connected to a first control node, and the fourth transistor is configured to control the level of the second node in response to a level of the first control node;
• a first electrode of the fifth transistor is connected to the first voltage line to receive the first voltage, a second electrode of the fifth transistor is connected to the second node, a gate electrode of the fifth transistor is connected to a reset signal line, and the fifth transistor is configured to reset the second node;
• and
• an active layer of the fourth transistor and an active layer of the fifth transistor extend in the first direction, respectively, and are arranged along a second direction, and the second direction intersects with the first direction.

A display substrate, comprising:

• a base substrate;
• and
• a gate driving circuit provided on a peripheral region of the base substrate, wherein the gate driving circuit comprises a plurality of shift register circuits that are arranged in a first direction,
• each shift register circuit comprises an input circuit, a control circuit, an output circuit and an output noise reduction circuit,
• the input circuit is connected to an input terminal and configured to control a level of a first node in response to an input signal that is input by the input terminal,
• the control circuit is connected to the first node, a second node and a third node,
• the output circuit is connected to the third node and an output terminal, respectively, and is configured to provide an output signal to the output terminal,
• the output noise reduction circuit is connected to the second node and the output terminal, respectively, and is configured for noise reduction on the output terminal,
• the control circuit comprises a first transistor, a second transistor and a third transistor,
• a first electrode of the first transistor is connected to the second node and configured to control a level of the second node,
• a first electrode of the second transistor is connected to the third node, a second electrode of the second transistor is connected to a first voltage line to receive a first voltage, a gate electrode of the second transistor is connected to the first node, and the second transistor is configured to control a level of the third node in response to the level of the first node,
• a first electrode of the third transistor is connected to the third node and configured to control the level of the third node, and
• at least two selected from group consisting of an active layer of the first transistor, an active layer of the second transistor and an active layer of the third transistor extend in the first direction and are sequentially arranged in the first direction,
• wherein the control circuit further comprises:
• a fourth transistor and a fifth transistor,
• a first electrode of the fourth transistor is connected to the first voltage line to receive the first voltage, a second electrode of the fourth transistor is connected to the second node, a gate electrode of the fourth transistor is connected to a first control node, and the fourth transistor is configured to control the level of the second node in response to a level of the first control node;
• a first electrode of the fifth transistor is connected to the first voltage line to receive the first voltage, a second electrode of the fifth transistor is connected to the second node, a gate electrode of the fifth transistor is connected to a reset signal line, and the fifth transistor is configured to reset the second node;
• and
• an active layer of the fourth transistor and an active layer of the fifth transistor extend in the first direction, respectively, and are arranged along a second direction, and the second direction intersects with the first direction.