Degradations detection for MOS-transistors and gate-drivers
AssigneesInfineon Technologies AG, Universita Degli Studi Di Milano-Bicocca
InventorsAlbino Pidutti, Jens Barrenscheen, Andrea Baschirotto, Paolo Del Croce, Ordwin Haase, Andre Mourrier
Life of this patent
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Abstract
In accordance with an embodiment, a method includes: generating a gate voltage for a field-effect transistor in response to an input signal; generating a pulse signal with a pulse length that corresponds to the time that it takes until the gate voltage attains a specific level transition in response to a corresponding level transition in the input signal; and monitoring the pulse signal to detect whether the pulse length is outside a specific range.
Claims20
A circuit comprising:
- a control circuit configured to generate a gate voltage for a field-effect transistor in response to an input signal;
- a pulse generator configured to generate a pulse signal, wherein the pulse signal has a pulse length that corresponds to a length of time from a level transition of the input signal to a specific level transition of the gate voltage in response to the level transition of the input signal;
- and
- a monitoring circuit configured to receive the pulse signal and to detect whether the pulse length is outside a specific range.
A method comprising:
- generating a gate voltage for a field-effect transistor in response to an input signal;
- generating a pulse signal with a pulse length that corresponds to a length of time from a level transition of the input signal to a specific level transition of the gate voltage in response to the level transition of the input signal;
- and
- monitoring the pulse signal to detect whether the pulse length is outside a specific range.
A circuit comprising:
- a pulse generator comprising a trigger input node and a pulse signal output node;
- a gate driver circuit having an input coupled to the pulse signal output node of the pulse generator and an output configured to be coupled to a control node of a switching transistor;
- a feedback circuit coupled between the output of the gate driver circuit and a pulse width adjustment input of the pulse generator, wherein the feedback circuit is configured to cause the pulse generator to generate a signal at the pulse signal output node having a pulse width corresponding to a length of time from a level transition of an input signal at the trigger input node to a specific level transition of a gate voltage at the output of the gate driver circuit in response to the level transition of the input signal;
- and
- a pulse width comparator having an input node coupled to the pulse signal output node of the pulse generator, and an output configured to indicate that the pulse width of the signal at the pulse signal output node of the pulse generator is outside of a first range of values.
Dependencies are inferred from the claim text.