AC coupling modules for bias ladders

A method of biasing a field-effect transistor (FET) switch stack, the method comprising:

• providing a plurality of series-coupled FETs, wherein each FET of the plurality of series-coupled FETs comprises a gate, wherein the plurality of series-coupled FETs comprises one or more series-coupled positive-logic FETs requiring a relative negative VGS to effectively turn OFF but configured to not require a negative voltage source, wherein the one or more series-coupled positive logic FETs are series-coupled on at least one end to an end-cap FET configured to turn OFF when the VGS of the end-cap FET is essentially zero volts;
• coupling a first gate bias resistor ladder to the plurality of series-coupled FETs, the first gate bias resistor ladder comprising a plurality of parallel-coupled variable-valued resistors, wherein each variable-valued resistor of the first gate bias resistor ladder is coupled to the gate of one corresponding FET of the plurality of series-coupled FETs;
• and
• coupling a second gate bias resistor ladder to the first gate bias resistor ladder, the second gate bias resistor ladder comprising a plurality of series-coupled constant-valued resistors, wherein each constant-valued resistors of the second gate bias resistor ladder is coupled to one corresponding variable-valued resistor of the first gate bias resistor ladder.

A method of biasing a field-effect transistor (FET) switch stack, the method comprising:

• providing a plurality of series-coupled FETs, wherein each FET of the plurality of series-coupled FETs comprises a gate, wherein the plurality of series-coupled FETs comprises one or more series-coupled positive-logic FETs requiring a relative negative VGS to effectively turn OFF but configured to not require a negative voltage source, wherein the one or more series-coupled positive logic FETs are series-coupled on at least one end to an end-cap FET configured to turn OFF when the VGS of the end-cap FET is essentially zero volts;
• coupling a first gate bias resistor ladder to the plurality of series-coupled FETs, the first gate bias resistor ladder comprising a plurality of parallel-coupled variable-valued resistors, wherein each variable-valued resistor of the first gate bias resistor ladder is coupled to the gate of one corresponding FET of the plurality of series-coupled FETs;
• and
• coupling a second gate bias resistor ladder to the first gate bias resistor ladder, the second gate bias resistor ladder comprising a plurality of series-coupled variable-valued resistors, wherein each valuable-valued resistor of the second gate bias resistor ladder is coupled to one corresponding variable-valued resistor of the first gate bias resistor ladder.