Memory physical layer interface, memory apparatus and method thereof

A memory physical layer interface, comprising:

• a multi-tap decision feedback equalization (DFE) receiver, comprising a plurality of DFE taps;
• and
• a tap reset circuit, generating a pulse signal and a reset signal in accordance with a gap interval between read bursts to reset the plurality of DFE taps during the gap interval between the read bursts,
• wherein the tap reset circuit is configured to reset the plurality of DFE taps of the multi-tap DFE receiver using the pulse signal in response to determining that the gap interval between read bursts is a first predetermined interval, the tap reset circuit is configured to reset the plurality of DFE taps of the multi-tap DFE receiver using the reset signal in response to determining that the gap interval between read bursts is a second predetermined interval, and the second predetermined interval is greater than the first predetermined interval.

A method of a memory apparatus comprising a memory device, a memory controller and a memory physical layer interface, the memory physical layer interface comprising a multi-tap decision feedback equalization (DFE) receiver and a tap reset circuit, the method comprising:

• generating a pulse signal and a reset signal in accordance with a gap interval between read bursts;
• resetting a plurality of DFE taps of the muti-tap DFE receiver using the pulse signal in response to determining that the gap interval between read bursts is a first predetermined interval;
• and
• resetting the plurality of DFE taps of the muti-tap DFE receiver using the reset signal in response to determining that the gap interval between read bursts is a second predetermined interval,
• wherein the second predetermined interval is greater than the first predetermined interval.