Crossbar circuit for unaligned memory access in neural network processor

A method of operating a neural processor circuit, comprising:

• storing, in a buffer memory of a data processor circuit, input data comprising a plurality of data elements, wherein a data element occupies a location of the buffer memory that is addressed by a data address;
• decoding, by an address decoder circuit of the data processor circuit, one or more address components of an address for the buffer memory including a most significant address component to generate a decoded address for the buffer memory to access a portion of input data comprising multiple data elements of the plurality of data elements;
• receiving, by a crossbar circuit, one or more address components including a least significant address component generated from the address for the buffer memory;
• receiving, by the crossbar circuit, the portion of input data from the buffer memory based on the decoded address during each operating cycle;
• re-aligning the multiple data elements of the portion of input data accessed by the decoded address or bypassing the portion of input data by the crossbar circuit during each operating cycle;
• receiving, at a neural engine circuit coupled to the crossbar circuit, at least a portion of the re-aligned or bypassed portion of input data, wherein the crossbar circuit is directly coupled to the data processor circuit and the neural engine circuit, bypassing cache or buffer components, to reduce power consumption by the neural engine circuit;
• and
• performing, by the neural engine circuit, a convolution operation on the received portion of re-aligned or bypassed portion of input data to generate output data.

An electronic device, comprising:

• a system memory storing input data;
• and
• a neural processor circuit coupled to the system memory, the neural processor circuit including:
• a data processor circuit, the data processor circuit comprising:
• a buffer memory configured to store input data comprising a plurality of data elements, wherein a data element occupies a location of the buffer memory that is addressed by a data address;
• and
• an address decoder circuit coupled to the buffer memory and configured to decode one or more address components of an address for the buffer memory including a most significant address component to generate a decoded address for the buffer memory to access a portion of input data comprising multiple data elements of the plurality of data elements;
• a crossbar circuit coupled to the data processor circuit and configured, during each operating cycle, to receive one or more address components of the address including a least significant address component, and further receive the portion of the input data from the buffer memory based on the decoded address, and re-align the multiple data elements of the portion of input data accessed by the decoded address or bypass the portion of input data, and
• a neural engine circuit coupled to the crossbar circuit, wherein the crossbar circuit is directly coupled to the data processor circuit and the neural engine circuit, bypassing cache or buffer components, to reduce power consumption by the neural engine circuit, the neural engine circuit configured to:
• receive at least a portion of the re-aligned or bypassed portion of input data, and
• perform a convolution operation on the received portion of re-aligned or bypassed portion of input data to generate output data.