Clock control device and clock control method for serial peripheral interface
AssigneeGigadevice Semiconductor Inc.
InventorAnbing Xiao
Life of this patent
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Abstract
A clock control device for a serial peripheral interface is disposed in a control device. The clock control device includes: a local delay module configured to delay a local clock signal to obtain a first delayed local clock signal; a clock selector configured to select one of the first delayed local clock signal and an external clock signal as a basic clock signal; and a first delay module configured to phase-delay the basic clock signal to obtain a delayed basic clock signal that can be used by the control device as a reception operating clock for sampling an external data signal transmitted by a storage device.
Claims20
A clock control device for a serial peripheral interface, wherein the clock control device is disposed in a control device communicable with a storage device through the serial peripheral interface, the clock control device comprising:
- a local delay module configured to receive a local clock signal of the control device, and delay the local clock signal to obtain a first delayed local clock signal;
- a clock selector configured to receive the first delayed local clock signal and an external clock signal, select one of the first delayed local clock signal and the external clock signal as a basic clock signal, and output the basic clock signal;
- and
- a first delay module configured to phase-delay the basic clock signal, to obtain a delayed basic clock signal as a reception operating clock for the control device to sample an external data signal transmitted by the storage device.
A clock control method for a serial peripheral interface, comprising:
- receiving a local clock signal and an external clock signal, and delaying the local clock signal to obtain a first delayed local clock signal;
- selecting, based on a clock selection control signal, one of the external clock signal and the first delayed local clock signal as a basic clock signal;
- and
- phase-delaying the basic clock signal, to obtain a delayed basic clock signal as a reception operating clock for a control device to sample an external data signal transmitted by a storage device.
Dependencies are inferred from the claim text.