Glitch-free power supply independent sequence circuit

A power supply independent sequence (PSIS) system comprising:

• a high-voltage input configured to receive a first voltage;
• a low-voltage input configured to receive a second voltage lower than the first voltage;
• a power check circuit configured to generate one or more power ok signals indicating that the first voltage or the second voltage is present, the power check circuit comprising
• a voltage threshold detection circuit coupled to the low-voltage input and configured to output a detected voltage that is zero when the second voltage is below a predefined threshold and that is the second voltage when the second voltage is at or above the predefined threshold,
• a glitch removal circuit coupled to the detected voltage and the high-voltage input, the glitch removal circuit comprising a voltage divider circuit configured to generate an internal voltage from the first voltage and lower than the first voltage, the glitch removal circuit being configured to
• output a missing low-voltage signal as high when the first voltage is received at the high-voltage input and the second voltage is below the predefined threshold, and
• output the missing low-voltage signal as low when the first voltage is received at the high-voltage input and the second voltage is at or above the predefined threshold, and
• a pull-down switch comprising a control input coupled to the missing low-voltage signal and configured to pull at least one of the one or more power ok signals to a reference ground voltage when the missing low-voltage signal is high;
• and
• an input/output circuit coupled to the one or more power ok signals and comprising communication circuitry, the input/output circuit being configured to disable the communication circuitry when the one or more power ok signals are low.

A power supply independent sequence (PSIS) system comprising:

• a high-voltage input configured to receive a first voltage;
• a low-voltage input configured to receive a second voltage lower than the first voltage;
• a power check circuit comprising
• a power sniffer circuit configured to generate one or more power ok signals indicating that the first voltage or the second voltage are present,
• a voltage threshold detection circuit coupled to the low-voltage input and configured to output a detected voltage that is zero when the second voltage is below a predefined threshold and that is the second voltage when the second voltage is at or above the predefined threshold,
• a glitch removal circuit coupled to the detected voltage and the high-voltage input, the glitch removal circuit configured to output a missing low-voltage signal as high when the first voltage is received at the high-voltage input and the second voltage is below the predefined threshold, and output the missing low-voltage signal as low when the first voltage is received at the high-voltage input and the second voltage is at or above the predefined threshold, and
• a pull-down switch comprising a control input coupled to the missing low-voltage signal and configured to pull at least one of the one or more power ok signals to a reference ground voltage when the missing low-voltage signal is high;
• and
• an input/output circuit coupled to the one or more power ok signals and comprising
• a power mux circuit configured to generate an intermediate voltage when one or both of the first voltage and the second voltage are non-zero, and
• communication circuitry comprising a transmission circuit and a reception circuit, the input/output circuit being configured to disable the communication circuitry when the one or more power ok signals are low.