Method and apparatus for memory testing

A memory testing apparatus, comprising:

• a clamp, configured to hold a plurality of dies to be tested;
• a storage device, configured to store a plurality of flags respectively corresponding to the plurality of dies;
• and
• a test control device, coupled to the clamp and the storage device, configured to detect a target memory cell corresponding to a tail bit of each of the plurality of dies,
• wherein, after the plurality of dies are idle for a first time, the test control device performs a first stage test on the plurality of dies, and sets the plurality of flags corresponding to the plurality of dies that fail the first stage test to a first logic level,
• after the plurality of dies are idle for a second time, the test control device performs a second stage test on the plurality of dies, and regards the plurality of dies that pass the second stage test and have the corresponding plurality of flags set to the first logical level as a plurality of suspected good dies and keeps the plurality of suspected good dies idle,
• after the plurality of suspected good dies are idle for a third time, the test control device performs a third stage test on the plurality of suspected good dies.