Processing system, related integrated circuit, device and method

A processing system comprising:

• a positive supply terminal and a negative supply terminal;
• and
• a sub-circuit comprising:
• a transmission terminal;
• a three-state driver circuit comprising:
• a first electronic switch connected between the transmission terminal and the positive supply terminal;
• and
• a second electronic switch connected between the transmission terminal and the negative supply terminal,
• wherein the three-state driver circuit comprises a combinational logic circuit configured to monitor logic levels of a first signal and a second signal, and selectively activate one of the following switching states as a function of the logic levels of the first signal and the second signal:
• in a first switching state, connect the transmission terminal to the positive supply terminal by closing the first electronic switch,
• in a second switching state, connect the transmission terminal to the negative supply terminal by closing the second electronic switch, and
• in a third switching state, put the transmission terminal in a high-impedance state by opening the first electronic switch and the second electronic switch;
• a CAN FD light controller configured to sequentially transmit bits of a CAN FD light frame, wherein the CAN FD light frame comprises:
• a start-of-frame bit,
• a sequence of bits comprising in sequence a Cyclic Redundancy Check (CRC), delimiter bit, an acknowledge bit, an acknowledge delimiter bit and an End-of-Frame field having 7 bits, and
• a plurality of intermediate bits between the start-of-frame bit and the CRC delimiter bit, and
• wherein the CAN FD light controller is configured to sequentially transmit, in a first operating mode, the bits of the CAN FD light frame by generating the first signal and the second signal in response to a transmission clock signal in order to:
• transmit the start-of-frame bit by activating the second switching state for one clock cycle,
• sequentially transmit the intermediate bits by sequentially selecting a bit of the intermediate bits and activating the first or second switching states as a function of the logic level of the selected bit, and
• once having transmitted the intermediate bits, activate the third switching state;
• and
• a reception terminal, wherein the CAN FD light controller is configured to sequentially receive the bits of a further CAN FD light frame via the reception terminal.

A method for operating a processing system comprising:

• sequentially transmitting bits of a CAN FD light frame in a commander/responder communication protocol, the commander/responder communication protocol comprising a CAN FD Light protocol, wherein the CAN FD light frame comprises:
• a start-of-frame bit,
• a sequence of bits comprising in sequence a Cyclic Redundancy Check (CRC) delimiter bit, an acknowledge bit, an acknowledge delimiter bit and an End-of-Frame field having 7 bits, and
• a plurality of intermediate bits between the start-of-frame bit and the CRC delimiter bit,
• wherein transmitting the bits of the CAN FD light frame comprises generating a first signal and a second signal of the processing system in response to a transmission clock signal in order to:
• transmit the start-of-frame bit by activating a second switching state for one clock cycle,
• sequentially transmit the intermediate bits by sequentially selecting a bit of the intermediate bits and activating a first switching state or the second switching state as a function of a logic level of a selected bit, and
• once having transmitted the intermediate bits, activate a third switching state, wherein generating the first signal and the second signal comprises:
• controlling a three-state driver circuit comprising:
• a first electronic switch connected between a transmission terminal and a positive supply terminal,
• a second electronic switch connected between the transmission terminal and a negative supply terminal, and
• a combinational logic circuit configured to monitor logic levels of the first signal and the second signal and selectively activate the first switching state by closing the first electronic switch, the second switching state by closing the second electronic switch, and the third switching state by opening both the first electronic switch and the second electronic switch.