Signal converter with delay architecture for concurrent signal processing
AssigneeUniversity of Southern California
InventorsShuo-Wei Chen, Mohsen Hassanpourghadi, Juzheng Liu
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Abstract
Aspects of this technical solution can include a plurality of SAR TC stages configured to convert an input time signal to a digital code including a plurality of output signals each corresponding to a SAR TDC stage among the plurality of SAR TDC stages connected to an input of a following SAR TDC stage among the plurality of SAR TDC stages, where the SAR stage is controlled by a clock signal based on a delayed clock signal from a previous SAR TDC stage among the plurality of SAR TDC stages.
Claims20
An analog-to-digital converter comprising:
- a pipelined successive approximation register (SAR) time-to-digital converters (TDC) device, comprising:
- a plurality of SAR TDC stages configured to convert an input time signal to a digital code including a plurality of output signals each corresponding to a SAR TDC stage among the plurality of SAR TDC stages connected to an input of a following SAR TDC stage among the plurality of SAR TDC stages,
- wherein the SAR stage is controlled by a clock signal based on a delayed clock signal from a previous SAR TDC stage among the plurality of SAR TDC stages;
- and
- a delay difference generation device comprising:
- a tunable delay cell having a delay based on an input digital code and modifiable in response to tuning one or more of a pull-up strength and a pull-down strength of an inverter by a switch.
A pipelined time-to-digital converters (TDC) method, the method comprising:
- converting, by a plurality of time-domain conversion stages, an input time-domain signal to a corresponding bit of a digital code in accordance with a cascade configuration;
- and
- transmitting, by a time-domain conversion stage among the plurality of time-domain conversion stages, an output time-domain signal of the time-domain conversion stage to an input of a following time-domain conversion stage among the plurality of time-domain conversion stages,
- wherein each stage is controlled by a clock signal based on a delayed clock signal from a previous time-domain conversion stage among the plurality of time-domain conversion stages.
A voltage-to-time converter (VTC) device, the device comprising:
- a common-mode capacitor coupled with a center node of one or more voltage sampling capacitors;
- and
- a current source coupled with the common-mode capacitor and configured to charge the common-mode capacitor.
Dependencies are inferred from the claim text.