Phase-locked loop (PLL) circuitry having phase interpolators with reduced power consumption
AssigneeApple Inc.
InventorsAnkit Srivastava, Ahmed I Hussein
Life of this patent
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Abstract
Phase-locked loop circuitry is provided that includes a time-to-digital converter, a first frequency divider circuit coupled to an output of the time-to-digital converter, and a second frequency divider circuit coupled between the first frequency divider circuit and an input of the time-to-digital converter and having a phase interpolator with a plurality of delay circuits forming a first digital-to-analog converter (DAC) circuit and a second digital-to-analog converter (DAC) circuit separate from the first DAC circuit. The phase interpolator can be calibrated using the time-to-digital converter.
Claims20
Phase-locked loop circuitry comprising:
- a time-to-digital converter;
- a first frequency divider circuit of a first divider type coupled to an output of the time-to-digital converter;
- and
- a second frequency divider circuit of a second divider type, different than the first divider type, coupled between the first frequency divider circuit and an input of the time-to-digital converter and having a phase interpolator with a plurality of delay circuits forming a first digital-to-analog converter (DAC) circuit and a second digital-to-analog converter (DAC) circuit separate from the first DAC circuit.
A method of operating phase-locked loop circuitry, comprising:
- with an oscillator, producing an output clock signal;
- with a frequency divider, receiving the output clock signal and outputting a plurality of clock signals;
- with a multiplexer, receiving the plurality of clock signals and selectively outputting first and second clock signals from among the plurality of clock signals;
- with a phase interpolator, receiving the first and second clock signals and outputting a feedback clock signal;
- and
- with a time-to-digital converter, receiving the first clock signal from the multiplexer and the feedback clock signal from the phase interpolator.
Phase-locked loop circuitry comprising:
- a time-to-digital converter;
- a first frequency divider circuit coupled to an output of the time-to-digital converter;
- and
- a second frequency divider circuit coupled between the first frequency divider circuit and an input of the time-to-digital converter and having a phase interpolator that includes a plurality of delay circuits forming a first digital-to-analog converter (DAC) circuit and a second digital-to-analog converter (DAC) circuit.
Dependencies are inferred from the claim text.