US 12,658,896 B2 · Integrated clock gate with circuitry to facilitate clock frequency division

Abstract

Techniques and mechanisms for an integrated clock gate (ICG) to selectively output a clock signal, and to provide frequency division functionality. In an embodiment, an ICG circuit comprises first circuitry which is coupled to receive a first clock signal, and second circuitry which is coupled to receive a control signal. The first circuitry provides a single edge triggered flip-flop functionality, and is coupled to communicate a feedback signal which the first circuitry is further coupled to receive. Based on the control signal and the feedback signal, the second circuitry performs an exclusive OR (XOR) operation to selectively enable the first circuitry to generate a second clock signal based on the first clock signal. In another embodiment, a frequency of the second clock signal is substantially equal to one half of a frequency of the first clock signal.

Claims20

Dependent claims

An integrated circuit (IC) die comprising:

a first clock gate circuit comprising:
a first flip-flop circuit to receive a first clock signal;
and
a first enablement circuit coupled to receive both a first feedback signal from the first flip-flop circuit and a first control signal, the first enablement circuit to generate, based on the first control signal and the first feedback signal, a first output to selectively enable the first flip-flop circuit to generate a second clock signal based on the first clock signal;
wherein the first output corresponds to a result of a first one or more Boolean operations comprising a first exclusive OR (XOR) operation based on the first control signal and the first feedback signal, and wherein a first frequency of the first clock signal is substantially equal to twice a second frequency of the second clock signal responsive to the first control signal being at a first logical state, and the first output is suspended at a low or high logical level responsive to the first control signal being at a second logical state that is different than the first logical state.

2 more elements

An integrated circuit (IC) die comprising:

a first clock gate circuit comprising:
a first flip-flop circuit to receive the first clock signal;
and
a first enablement circuit coupled to receive both a first feedback signal from the first flip-flop circuit and a first control signal, the first enablement circuit to generate, based on the first control signal and the first feedback signal, a first output to selectively enable the first flip-flop circuit to generate a second clock signal based on the first clock signal;
wherein, based on the first feedback signal, a first frequency of the first clock signal is substantially equal to twice a second frequency of the second clock signal responsive to the first control signal being at a first logical state, and the first output is suspended at a low or high logical level responsive to the first control signal being at a second logical state that is different than the first logical state;
a first multi-bit flip-flop unit coupled to communicate first data based on the second clock signal, wherein the first multi-bit flip-flop circuit comprises double edge triggered flip-flops.

3 more elements

A system comprising:

a memory;
a processor coupled to the memory, the processor comprising:
a first clock gate circuit comprising:
a first flip-flop circuit to receive the first clock signal;
and
a first enablement circuit coupled to receive both a first feedback signal from the first flip-flop circuit and a first control signal, the first enablement circuit to generate, based on the first control signal and the first feedback signal, a first output to selectively enable the first flip-flop circuit to generate a second clock signal based on the first clock signal;
wherein the first output corresponds to a result of a first one or more Boolean operations comprising a first exclusive OR (XOR) operation based on the first control signal and the first feedback signal, and wherein a first frequency of the first clock signal is substantially equal to twice a second frequency of the second clock signal responsive to the first control signal being at a first logical state, and the first output is suspended at a low or high logical level responsive to the first control signal being at a second logical state that is different than the first logical state;
and
a wireless interface to enable the processor to communicate with another device.

6 more elements

Dependencies are inferred from the claim text.

Integrated clock gate with circuitry to facilitate clock frequency division

Life of this patent

Integrated clock gate with circuitry to facilitate clock frequency division

Life of this patent

Abstract

Claims20