Method for manufacturing wiring board, and wiring board
OwnerKei Togasaki, Kazuyuki Mitsukura +4inventors
InventorsKei Togasaki, Kazuyuki Mitsukura, Masaya Toba, Kenichi Iwashita, Keishi Ono, Mao Narita
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Abstract
A method for manufacturing a wiring board, including: forming a resist layer on a seed layer comprising a metal provided on a support body; forming a pattern including an opening to which the seed layer is exposed in the resist layer by light exposure and development of the resist layer; and forming a copper plating layer on the seed layer exposed into the opening by electrolytic plating, in this order. The arithmetic mean roughness Ra of the surface of the seed layer on a side opposite to the support body is 0.05 μm or more and 0.30 μm or less.
Claims10
A method for manufacturing a wiring board, comprising:
- forming a resist layer on a seed layer comprising a metal provided on a support body;
- forming a pattern including an opening to which the seed layer is exposed in the resist layer by light exposure and development of the resist layer;
- and
- forming a copper plating layer on the seed layer exposed into the opening by electrolytic plating, in this order,
- wherein arithmetic mean roughness Ra of a surface of the seed layer on a side opposite to the support body is adjusted in a range of 0.05 um or more and 0.30 um or less such that a number of black portions with a width of less than 0.3 um observed in the copper plating layer in a vicinity of an interface between the seed layer and the copper plating layer is 9.0 or less per a width of 1 μm in a direction parallel to a main surface of the support body.
A wiring board comprising:
- a support body;
- and
- wiring including a seed layer comprising a metal provided on the support body, and a copper plating layer formed by electrolytic plating,
- wherein arithmetic mean roughness Ra of a surface of the seed layer on a side opposite to the support body is 0.05 um or more and 0.30 um or less, and
- wherein a number of black portions with a width of less than 0.3 um observed in the copper plating layer in a vicinity of an interface between the seed layer and the copper plating layer is 9.0 or less per a width of 1 μm in a direction parallel to a main surface of the support body.
Dependencies are inferred from the claim text.