Buffer circuit for driving a GAN power switch and corresponding driver circuit

A driver circuit, comprising:

• an input supply pad configured to receive a supply voltage, an input ground pad configured to receive a ground voltage, an input high-side control pad configured to receive a high-side control signal, an input low-side control pad configured to receive a low-side control signal, and an output pad configured to produce an output driving signal;
• a high-side output buffer circuit;
• a low-side output buffer circuit;
• a level shifter configured to shift and pass the high-side control signal to the high-side output buffer circuit;
• a low-side intermediate buffer circuit configured to pass the low-side control signal to the low-side output buffer circuit;
• a high-side GaN power transistor arranged between a high-voltage supply pad and the output pad and driven by the high-side output buffer circuit;
• a low-side GaN power transistor arranged between the output pad and a protected ground pad and driven by the low-side output buffer circuit, wherein the low-side intermediate buffer circuit includes an input stage, a differential-to-single-ended stage, and an output stage, wherein the input stage includes:
• an input differential pair of transistors, a first transistor of the pair being configured to receive an input signal at a control terminal thereof, and a second transistor of the pair being configured to receive a reference signal at a control terminal thereof;
• a first current generator load coupled between the first transistor and a supply node of the low-side intermediate buffer circuit;
• a second current generator load coupled between the second transistor and the supply node of the low-side intermediate buffer circuit;
• and
• a tail current generator coupled between a tail node of the input differential pair of transistors and a ground node of the low-side intermediate buffer circuit;
• and wherein the differential-to-single-ended stage includes a current mirror arrangement coupled to first and second output nodes of the input differential pair of transistors;
• and wherein the output stage includes a pair of cascaded inverter circuits, the first inverter circuit being configured to receive a single-ended signal from an output node of the differential-to-single-ended stage, and the second inverter circuit being configured to receive a complemented signal from an output node of the first inverter circuit to produce an output signal of the low-side intermediate buffer circuit.