Input buffer circuit
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsYu-Kai Tsai, Chia-Hui Chen, Chia-Jung Chang
Life of this patent
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Abstract
An integrated circuit includes an upper threshold circuit configured to set a logic level of a first enabling signal, a lower threshold circuit configured to set a logic level of a second enabling signal, and a control circuit configured to change an output voltage signal in response to a condition that the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively. In the control circuit, a first switch is electrically connected to a second switch at a buffer output node. The control circuit includes a regenerative circuit configured to maintain the output voltage signal at the buffer output node while each of the first switch and the second switch is at a disconnected state.
Claims20
An integrated circuit comprising:
- an upper threshold circuit configured to set a logic level of a first enabling signal in response to an input voltage signal rising across an upper threshold voltage;
- a lower threshold circuit configured to set a logic level of a second enabling signal in response to the input voltage signal falling across a lower threshold voltage;
- and
- a control circuit configured to change an output voltage signal from a first voltage level to a second voltage level in response to a condition that the logic level of the first enabling signal and the logic level of the second enabling signal are changed consecutively, wherein the control circuit comprises,
- a first switch configured to receive the first enabling signal from the upper threshold circuit,
- a buffer output node electrically connected to the first switch,
- a second switch electrically connected to the first switch at the buffer output node and configured to receive the second enabling signal from the lower threshold circuit, and
- a regenerative circuit electrically coupled to the buffer output node and configured to maintain the output voltage signal at the buffer output node while each of the first switch and the second switch is at a disconnected state.
A method comprising:
- generating a first enabling signal in response to an input voltage signal rising across an upper threshold voltage;
- generating a second enabling signal in response to the input voltage signal falling across a lower threshold voltage;
- controlling a first switch with the first enabling signal;
- controlling a second switch with the second enabling signal, wherein the second switch is connected to the first switch at a buffer output node;
- and
- changing an output voltage signal from a first voltage level to a second voltage level in response to a condition that each of the first enabling signal and the second enabling signal changes a logical level consecutively, wherein changing the output voltage signal comprises maintaining the output voltage signal at the buffer output node with a regenerative circuit while each of the first switch and the second switch is at a disconnected state.
An integrated circuit comprising:
- an upper threshold circuit configured to set a logic level of a first enabling signal in response to an input voltage signal rising across an upper threshold voltage;
- a lower threshold circuit configured to set a logic level of a second enabling signal in response to the input voltage signal falling across a lower threshold voltage;
- a first switch configured to receive the first enabling signal from the upper threshold circuit;
- a buffer output node electrically connected to the first switch;
- a second switch electrically connected to the first switch at the buffer output node and configured to receive the second enabling signal from the lower threshold circuit;
- and
- a regenerative circuit electrically coupled to the buffer output node and configured to maintain an output voltage signal at the buffer output node while each of the first switch and the second switch is at a disconnected state.
Dependencies are inferred from the claim text.