Failsafe input-output circuit

An electronic circuit comprising:

• an input-output (IO) terminal;
• a supply terminal;
• a reference terminal;
• a high-side transistor having a current path coupled between the supply terminal and the IO terminal;
• a low-side transistor having a current path coupled between the IO terminal and the reference terminal;
• a driver having an input and an output, the output of the driver coupled to a control terminal of the high-side transistor;
• and
• a bias generation circuit having an output coupled to a bulk terminal of the high-side transistor;
• wherein the bias generation circuit comprises:
• a latch having a first node and a second node;
• a first transistor having a control terminal coupled to the supply terminal, and a current path coupled between the IO terminal and the first node of the latch;
• a second transistor having a control terminal coupled to the second node of the latch, and a current path coupled between the IO terminal and the output of the bias generation circuit;
• and
• a third transistor having a control terminal coupled to the input of the latch, and a current path coupled between the supply terminal and the output of the bias generation circuit.

A system comprising:

• an input-output (IO) terminal;
• a supply terminal;
• a reference terminal;
• a high-side transistor having a current path coupled between the supply terminal and the IO terminal;
• a low-side transistor having a current path coupled between the IO terminal and the reference terminal;
• a driver having an input and an output, the input coupled to receive an input signal and an enable signal, the output of the driver coupled to the high-side transistor;
• and
• a bias generation circuit having an output coupled to the high-side transistor;
• wherein the bias generation circuit is configured to:
• determine an IO signal having a first value at the IO terminal;
• generate a bias signal having a second value based on the first value of the IO signal at the IO terminal;
• and
• provide the bias signal to the driver;
• and
• wherein the driver is configured to:
• based on a first state of the enable signal, provide the input signal to the IO terminal via the high-side transistor;
• and
• based on a second state of the enable signal, gate the input signal from being provided from the driver to the IO terminal and gate the IO signal from being provided from the IO terminal to the supply terminal based on providing a control signal to the high-side transistor, the control signal having a third value based on the second value of the bias signal.