Bit line voltage clamping read circuit for an in- memory compute operation where simultaneous access is made to plural rows of a static random access memory (SRAM)

An in-memory computation circuit, comprising:

• a memory array including memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, and each column including a true bit line connected to the memory cells of the column and a false bit line connected to the memory cells of the column;
• a word line driver circuit for each row having an output connected to drive the word line of the row;
• a row controller circuit configured to simultaneously actuate the word lines by applying pulses through the word line driver circuits to the word lines in response to feature data for an in-memory compute operation;
• and
• a column processing circuit including a true first read circuit coupled to each true bit line and a false read circuit coupled to each false bit line,
• wherein each true read circuit comprises:
• a first differential amplifier having a first input coupled to the true bit line, a second input configured to receive a reference voltage, and an output;
• wherein said reference voltage is at a level greater than a write margin voltage for the memory cells where the memory cells risk inadvertent bit flip during the simultaneous actuation of the word lines for the in-memory compute operation;
• a first MOS transistor having a drain coupled to the true bit line to receive a first read current and a gate coupled to the output of the first differential amplifier;
• a second MOS transistor having a gate coupled to the output of the first differential amplifier and a drain configured to output a first mirrored read current;
• and
• a first integration capacitor configured to integrate the first mirrored read current to generate a first output voltage, and
• wherein each false read circuit comprises:
• a second differential amplifier having a first input coupled to the false bit line, a second input configured to receive said reference voltage, and an output;
• a third MOS transistor having a drain coupled to the false bit line to receive a second read current and a gate coupled to the output of the second differential amplifier;
• and
• a fourth MOS transistor having a gate coupled to the output of the second differential amplifier and a drain configured to output a second mirrored read current;
• and
• a second integration capacitor configured to integrate the second mirrored read current to generate a second output voltage.