Clock monitoring circuit

A clock monitoring circuit configured to monitor a selection clock signal, the clock monitoring circuit comprising:

• a clock enable signal generator configured to generate a high-frequency clock enable signal, a low-frequency clock enable signal, and an ultra-high frequency clock enable signal based on a clock enable control signal and a reference clock signal;
• a high-frequency detector configured to generate a high-frequency count value by counting the selection clock signal based on the high-frequency clock enable signal and generate a high-frequency determination signal, which indicates whether the selection clock signal is a high-frequency signal, based on the high-frequency count value;
• a low-frequency detector configured to generate a low-frequency count value by counting the selection clock signal based on the low-frequency clock enable signal and generate a low-frequency determination signal based on the low-frequency count value, the low-frequency determination signal indicating whether the selection clock signal is a low-frequency signal;
• an ultra-high frequency detector configured to generate an ultra-high frequency determination signal based on the selection clock signal, the ultra-high frequency clock enable signal, and the reference clock signal, the ultra-high frequency determination signal indicating whether the selection clock signal is an ultra-high frequency signal;
• and
• a random frequency detector configured to generate a random frequency determination signal based on the high-frequency clock enable signal and the high-frequency count value, the random frequency determination signal indicating whether frequency shift has occurred to the selection clock signal.