Antifuse-type non-volatile memory cell
AssigneeeMemory Technology Inc.
InventorYi-Hung Li
Life of this patent
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Abstract
An antifuse-type non-volatile memory cell includes a select transistor, a following transistor and a capacitor. The first drain/source terminal of the select transistor is connected with a bit line. The gate terminal of the select transistor is connected with a word line. A first drain/source terminal of the following transistor is connected with a second drain/source terminal of the select transistor. A gate terminal of the following transistor is connected with a following line. A second drain/source terminal of the following transistor is connected with a first terminal of the capacitor. A second terminal of the capacitor is connected with an antifuse control line.
Claims15
An antifuse-type non-volatile memory cell, comprising:
- a semiconductor substrate;
- a well region formed in the semiconductor substrate;
- a first gate structure, a second gate structure and a third gate structure formed over a surface of the well region;
- a first doped region, a second doped region and a third doped region, wherein the first doped region is formed under the surface of the well region and arranged beside a first side of the first gate structure, the second doped region is formed under the surface of the well region and arranged between a second side of the first gate structure and a first side of the second gate structure, and the third doped region is formed under the surface of the well region and arranged between a second side of the second gate structure and a first side of the third gate structure;
- a first protecting layer, wherein a surface of the second doped region and a surface of the third doped region are completely covered by the first protecting layer to prevent a formation of electrical contact layers on the surfaces of the second doped region and the third doped region;
- a first electrical contact layer, a second electrical contact layer, a third electrical contact layer and a fourth electrical contact layer contacted with a surface of the first doped region, the first gate structure, the second gate structure and the third gate structure, respectively;
- and
- a first conducting line, a second conducting line, a third conducting line and a fourth conducting line electrically connected with the first electrical contact layer, the second electrical contact layer, the third electrical contact layer and the fourth electrical contact layer, respectively,
- wherein the well region, the first gate structure, the first doped region and the second doped region are collaboratively formed as a first select transistor, the well region, the second gate structure, the second doped region and the third doped region are collaboratively formed as a following transistor, and the third gate structure and the third doped region are collaboratively formed as a capacitor, wherein the antifuse-type non-volatile memory cell comprises the first select transistor, the first following transistor and the capacitor.
Dependencies are inferred from the claim text.