Clock signal frequency divider, processing system, processing device, and clock signal frequency dividing method

A processing device comprising:

• a clock signal reception circuit configured to receive a first clock signal, the first clock signal being a clock signal including a repetition of a periodic pattern signal in which a predetermined pulse of a mask pulse number is masked among consecutive pulses of a periodic pulse number the periodic pattern signal including a marker portion including at least one unmasked pulse at a start portion of the periodic pattern signal, the mask pulse number being smaller than the periodic pulse number, the periodic pattern signal being a clock signal in which a pattern of a timing of the at least one unmasked pulse of the marker portion does not appear in a portion other than a portion corresponding to the marker portion in the clock signal;
• a start specifying circuit configured to specify a start clock timing of the marker portion of the received first clock signal based on information regarding the marker portion in a case where the mask pulse number is equal to the mask pulse number of the first clock signal, the start clock timing being a first timing among timings at which the pulses are output as the clock signals in a case where the pulses are not masked;
• a clock information reception circuit configured to receive information regarding the mask pulse number of a second clock signal which is the clock signal whose mask pulse number is different from the mask pulse number of the first clock signal;
• a matching timing specifying circuit configured to specify a matching timing at which a timing of the unmasked pulse of the first clock signal and a timing of the unmasked pulse of the second clock signal match each other from the start clock timing, a pattern of the timing of the unmasked pulse of the first clock signal, and a pattern of the timing of the unmasked pulse of the clock signal in a case where the mask pulse number is equal to the mask pulse number of the second clock signal;
• and
• a communication circuit configured to communicate, at the specified matching timing, with a second information processing device to which the second clock signal is supplied.

A clock signal frequency dividing method comprising:

• generating, from pulses of a received input clock signal, an output clock signal including a repetition of a periodic pattern signal in which a pulse of a mask pulse number is masked among consecutive pulses of a periodic pulse number, the periodic pattern signal including a marker portion including at least one unmasked pulse at a start portion of the periodic pattern signal, the mask pulse number being smaller than the periodic pulse number;
• and
• outputting the output clock signal,
• wherein in the generating of the output clock signal, the periodic pattern signal is generated in such a way that a pattern of a timing of the at least one unmasked pulse of the marker portion does not appear in a portion other than a portion corresponding to the marker portion in the output clock signal.