Battery pack controller and control method

A battery pack control method that comprises:

• monitoring a current path through an array of one or more battery cells for a fault condition;
• monitoring a battery pack load terminal to detect when a voltage of the battery pack load terminal indicates a load condition;
• monitoring a battery pack charge terminal to detect when a voltage of the battery pack charge terminal indicates a charge condition;
• responsive to detecting the load condition and in the absence of a fault condition, asserting a discharge transistor control pin after ramping a voltage or current of a discharge transistor control pin for at least 10 ms;
• and
• responsive to detecting the charge condition, partially asserting a charge transistor control pin for at least 30 s if the array of one or more battery cells is depleted and otherwise asserting the charge transistor control pin.

A battery pack that comprises:

• a battery cell array;
• a charge transistor configured to control a charging current flow to the battery cell array from a battery pack charge terminal;
• a discharge transistor configured to control a load current flow from the battery cell array to a battery pack load terminal;
• a battery pack controller that includes:
• a fault detection circuit configured to detect a fault condition of the battery cell array;
• a monitor circuit configured to detect when a voltage of the battery pack load terminal indicates a load condition and configured to detect when a voltage of the battery pack charge terminal indicates a charge condition;
• a switch control circuit configured to selectively de-assert a discharge transistor control pin, assert the discharge transistor control pin, and ramp a voltage or current of the discharge transistor control pin in an open loop fashion for at least 10 ms, and configured to selectively de-assert a charge transistor control pin, assert the charge transistor control pin, and partially assert the charge transistor control pin for at least 30 s;
• and
• a status detection circuit configured to, in the absence of the fault condition, cause the switch control circuit to perform said ramping responsive to detection of the load condition while the discharge transistor control pin is de-asserted, and, responsive to detection of the charge condition, to cause the switch control circuit to partially assert the charge transistor control pin for at least 30 s if the battery cell array is depleted and otherwise to cause the switch control circuit to assert the charge transistor control pin.