Self-resetting clock generator

A system comprising:

• a memory device including a self-resetting clock generator circuit, the self-resetting clock generator circuit comprising:
• a keeper-free clock gate configured to generate a positive clock (PCLK) signal based on an enable (ENBL) signal, a reset (RST) signal, and an external clock (SOC CLK);
• a first bank of transistors configured to assert a self-timed clock signal (ST CLK #);
• and
• a second bank of transistors in parallel with the first bank of transistors and configured to de-assert (1→0) ST CLK # based on PCLK assertion (0→1).

A method for generating a clock signal for a memory, the method comprising:

• generating, by a keeper-free clock gate, a positive clock (PCLK) signal based on an enable (ENBL) signal, a reset (RST) signal, the PCLK fed back as input, and an external clock (SOC CLK);
• de-asserting self-timed clock signal (ST CLK #) based on assertion of the PCLK;
• and
• asserting an self-timed clock signal (ST CLK) based on de-assertion of the ST CLK #.