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US 12,627,283 B2Granted
Circuit for detecting timing violations in a digital circuit
AssigneeDolphin Semiconductor
InventorsMathieu Louvat, François Jacquet
Life of this patent
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Abstract
The present disclosure relates to a circuit comprising: —a first timing guard circuit (200) configured to detect when a slack time of a first data signal arriving at a first synchronous device (202) falls below a first threshold (SLG DELAY); and —a second timing guard circuit (200) configured to detect when a slack time of a second data signal arriving at a second synchronous device (202) falls below a second threshold (SLG DELAY), the first and second thresholds being different from each other.
Claims13
A circuit comprising:
- a plurality of first timing guard circuits each configured to detect when a slack time of a first data signal arriving at a first synchronous device falls below a first threshold;
- a second timing guard circuit configured to detect when a slack time of a second data signal arriving at a second synchronous device falls below a second threshold, the first and second thresholds being different from each other;
- and
- a timing response circuit configured to:
- receive status flag signals from the plurality of first timing guard circuits when the slack time of the first data signal falls below the first threshold;
- compare a number of flags signals generated by the plurality of first timing guard circuits with a threshold;
- and
- apply, in response to the number of flag signal exceeding the threshold, a first supply voltage or biasing voltage adjustment and/or a first frequency reduction to a clock signal of the circuit.
5 more elements
A method of timing control in a circuit, the method comprising:
- detecting, by each of a plurality of first timing guard circuits, when a slack time of a first data signal arriving at a first synchronous device falls below a first threshold;
- detecting, by a second timing guard circuit, when a slack time of a second data signal arriving at a second synchronous device falls below a second threshold, the first and second thresholds being different from each other;
- receiving, by the timing response circuit, status flag signals from the plurality of first timing guard circuits when the slack time of the first data signal falls below the first threshold;
- comparing, by the timing response circuit, a number of flag signals generated by the plurality of first timing guard circuits with a threshold;
- and
- applying, by the timing response circuit in response to the number of flag signals exceeding the threshold, a first supply voltage or biasing voltage adjustment and/or a first frequency reduction to a clock signal of the circuit.
3 more elements
A circuit comprising:
- a first timing guard circuit configured to detect when a slack time of a first data signal arriving at a first synchronous device falls below a first threshold;
- a plurality of second timing guard circuits each configured to detect when a slack time of a second data signal arriving at a second synchronous device falls below a second threshold, the first and second thresholds being different from each other;
- and
- a protection circuit configured to:
- receive alarm flag signals from the plurality of second timing guard circuits when the slack time of the second data signal falls below the second threshold;
- and
- apply, in response to the alarm signal from any of the second timing guard circuits, a second frequency reduction to a clock signal of the circuit.
4 more elements
Dependencies are inferred from the claim text.