Pointer information encoded in weighted increment signals

A synchronizing first-in-first-out buffer, comprising:

• an input port that receives a plurality of input words of data from a plurality of input ports and selects a storage element of a plurality of storage elements to which to provide each input word of data of the plurality of input words of data, wherein the plurality of input words of data are in a first clock domain;
• a pointer generation and synchronization circuit having an input to receive an input clockwide pulse generated in the first clock domain, the pointer generation and synchronization circuit comprising:
• a first pulse-to-pulse synchronizer circuit to convert at least a portion of the input clockwide pulse into an output clockwide pulse that is synchronized to a second clock domain, wherein the first pulse-to-pulse synchronizer circuit is configured to weight at least a portion of the output clockwide pulse by a first value that is greater than one;
• a first pointer counter having an input coupled to an output of the first pulse-to-pulse synchronizing circuit, to advance a count in response to receiving the output clockwide pulse that is synchronized to the second clock domain by a value that is at least equal to the first value;
• and
• a second pointer counter to receive a pointer generated in the second clock domain;
• and
• an output port to receive the plurality of input words of data from the plurality of storage elements and to receive the pointer generated in the second clock domain and to generate an output word of data selected from among the plurality of input words of data based on the pointer generated in the second clock domain.

A method, comprising:

• receiving an electronic signal including a first plurality of clockwide pulses in a first clock domain that runs at a first clock frequency;
• converting a first portion of the electronic signal to a first clockwide pulse in a second clock domain that runs at a second clock frequency, using a first pulse-to-pulse synchronizer circuit of a bank of pulse-to-pulse synchronizer circuits, wherein the first pulse-to-pulse synchronizer circuit weights the first clockwide pulse by a first value, and wherein the first value is greater than one;
• converting a second portion of the electronic signal to a second clockwide pulse in the second clock domain, using a second pulse-to-pulse synchronizer circuit of the bank of pulse-to-pulse synchronizer circuits, wherein the second pulse-to-pulse synchronizer circuit weights the second clockwide pulse by a second value that is equal to one;
• advancing a count of a pointer counter in response to the first clockwide pulse, where the count is advanced by a number that is equal to a sum of the first value and the second value;
• and
• outputting a pointer associated with the electronic signal based on the count.