Decoding acceleration with hardware decoder

A computing system to accelerate JPEG (Joint Photographic Experts Group) image decoding, the computing system comprising:

• a processor;
• and
• a decoder accelerator coupled to the processor via a decoder bus interface,
• wherein the processor is operable to:
• parse a JPEG file to obtain a header including one or more quantization tables and a plurality of Huffman code tables;
• load the plurality of Huffman code tables into the decoder accelerator via the decoder bus interface;
• transmit encoded data in the JPEG file to the decoder accelerator via the decoder bus interface;
• receive a set of accelerator-decoded JPEG data blocks from the decoder accelerator via the decoder bus interface;
• dequantize the set of accelerator-decoded JPEG data blocks that were previously decoded by the decoder accelerator using the one or more quantization tables to generate a set of dequantized JPEG data blocks;
• perform inverse discrete cosine transform on the set of dequantized JPEG data blocks that were previously decoded by the decoder accelerator to generate a set of spatial JPEG data blocks;
• and
• perform color conversion on the set of spatial JPEG data blocks to generate image data from the JPEG file, and
• wherein the decoder accelerator is operable to:
• store the plurality of Huffman code tables provided from the processor;
• receive the encoded data in the JPEG file from the processor;
• generate the accelerator-decoded JPEG data blocks using the Huffman code tables;
• and
• transmit the accelerator-decoded JPEG data blocks to the processor.