Semiconductor structure and manufacturing method thereof

A manufacturing method of a semiconductor structure, comprising:

• providing a substrate;
• and
• forming first transistor columns and second transistor columns on the substrate, wherein the first transistor columns and the second transistor columns are alternately arranged, a first transistor column comprises a plurality of first transistors arranged in a first direction, a second transistor column comprises a plurality of second transistors arranged in the first direction, the plurality of first transistors in the first transistor column are electrically connected to the plurality of second transistors in the second transistor column in one-to-one correspondence;
• wherein a length direction of a first transistor is same as a length direction of a second transistor, and a center of the first transistor is offset from a center of the second transistor in the first direction;
• wherein forming the first transistor columns and the second transistor columns on the substrate comprises:
• etching the substrate to form first wall-like structures extending in the first direction and second wall-like structures extending in the first direction, wherein the first wall-like structures and the second wall-like structures are alternately arranged in a second direction;
• etching the first wall-like structures to form a plurality of first openings in a first wall-like structure, wherein the plurality of first openings disconnect the first wall-like structure into a plurality of first active areas;
• and
• etching the second wall-like structures to form a plurality of second openings in a second wall-like structure, wherein the plurality of second openings disconnect the second wall-like structure into a plurality of second active areas, a center of a second opening is offset from a center of a first opening in the first direction, and a center of a first active area is offset from a center of a second active area in the first direction;
• wherein the first direction and the second direction are paralleled to a top surface of the substrate, the first direction and the second direction are intersected;
• further comprising:
• after forming the first active areas and the second active areas,
• doping the first active areas and the second active areas to form a first channel, and a first electrode and a second electrode on either side of the first channel in each of the first active areas, and to form a second channel, and a first electrode and a second electrode on either side of the second channel in each of the second active areas, wherein a direction from the first electrode of the first active area to the second electrode of the first active area is same as a direction from the first electrode of the second active area to the second electrode of the second active area;
• and
• forming gates covering the first channel and the second channel;
• further comprising:
• after forming first transistor columns and second transistor columns on the substrate,
• forming a first filling layer, which fills gaps between the first transistors and the second transistors and covers the first transistors and the second transistors;
• forming at least one first contact plug and at least one second contact plug penetrating through the first filling layer, wherein a bottom of the first contact plug is electrically connected to a gate of the first transistor, and a bottom of the second contact plug is electrically connected to a second electrode of the second transistor;
• and
• forming at least one interconnect line, wherein either ends of each interconnect line are electrically connected to a top of the first contact plug and a top of the second contact plug adjacent to the first contact plug, respectively.