Input buffer circuit having a signal splitter and combiner circuit

An input circuit configured to receive an input voltage and generate a digital output, comprising:

• a first signal splitter configured to generate a lower signal which tracks the input voltage in a range of a first voltage level and a second voltage level and provide a first control signal based on the lower signal;
• a second signal splitter configured to generate an upper signal which tracks the input voltage in a range of the second voltage level and a third voltage level and provide at least one control signal based on the upper signal, wherein the third voltage level is greater than the second voltage level, and the second level is greater than the first voltage level;
• a level shifter configured to receive the at least one control signal from the second signal splitter and provide a third control signal;
• and
• a combiner circuit configured to generate the digital output as a logical combination of the first and third controls signals, wherein the level shifter comprises:
• a first p-channel transistor coupled between a first voltage supply terminal configured to provide the third voltage level and a first circuit node, and having a control electrode coupled to receive one of the at least one control signal;
• a second p-channel transistor coupled between the first voltage supply terminal and a second circuit node, and having a control electrode coupled to receive another one of the at least one control signal;
• a first n-channel transistor having a first current electrode coupled to the first circuit node, a control electrode coupled to the second circuit node, and a second current electrode code coupled to a second voltage supply terminal configured to provide the first voltage level;
• and
• a second n-channel transistor having a first current electrode coupled to the second circuit node, a control electrode coupled to the first circuit node, and a second current electrode coupled to the second voltage supply terminal, wherein the second circuit node provides the second control signal.

An input circuit configured to receive an input voltage and generate a digital output, comprising:

• a first signal splitter configured to generate a lower signal which tracks the input voltage in a range of a first voltage level and a second voltage level, and having a first inverter configured to receive the lower signal and generate a first control signal which varies between the first and second voltage levels;
• a second signal splitter configured to generate an upper signal which tracks the input voltage in a range of the second voltage level and a third voltage level and having a first inverter configured to receive the upper signal and generate a second control signal which varies between the second and third voltage levels, wherein the third voltage level is greater than the second voltage level, and the second level is greater than the first voltage level;
• a level shifter configured to receive at least one control signal based on the second control signal and provide a third control signal which varies between the first and second voltage levels;
• and
• a combiner circuit configured to receive the third control signal, receive a fourth control signal based on the first control signal, and generate the digital output as a logical combination of the third and fourth controls signals,
• wherein the combiner circuit is coupled between a first voltage supply terminal configured to provide the second voltage level and a second voltage supply terminal configured to provide the first voltage level, the combiner circuit comprising:
• a first p-channel transistor having a first current electrode coupled to the first voltage supply terminal;
• a second p-channel transistor having a first current electrode coupled to a second current electrode of the first p-channel transistor, and a second current electrode coupled to a circuit node;
• a first n-channel transistor having a first current electrode coupled to the circuit node;
• and
• a second n-channel transistor having a first current electrode coupled to a second current electrode of the first n-channel transistor, and a second current electrode coupled to the second voltage supply terminal,
• wherein control electrodes of the first p-channel transistor and the second n-channel transistor are coupled to receive the third control signal, and control electrodes of the second p-channel transistor and the first n-channel transistor are coupled to receive the fourth control signal, and
• wherein the digital output signal is generated based on the circuit node.

An input circuit configured to receive an input voltage and generate a digital output, comprising:

• a first signal splitter configured to generate a lower signal which tracks the input voltage in a range of a first voltage level and a second voltage level, and having a first inverter configured to receive the lower signal and generate a first control signal which varies between the first and second voltage levels;
• a second signal splitter configured to generate an upper signal which tracks the input voltage in a range of the second voltage level and a third voltage level and having a first inverter configured to receive the upper signal and generate a second control signal which varies between the second and third voltage levels, wherein the third voltage level is greater than the second voltage level, and the second level is greater than the first voltage level;
• a level shifter configured to receive at least one control signal based on the second control signal and provide a third control signal which varies between the first and second voltage levels;
• and
• a combiner circuit configured to receive the third control signal, receive a fourth control signal based on the first control signal, and generate the digital output as a logical combination of the third and fourth controls signals,
• wherein:
• the first signal splitter comprises at least one additional inverter coupled to the output of the first inverter of the first signal splitter to generate the fourth control signal;
• and
• the second signal splitter comprises at least one additional inverter coupled to the output of the first inverter of the second signal splitter to generate the at least one control signal based on the second control signal for the level shifter.