Dynamic D flip-flop, register, chip, and data processing apparatus

A dynamic D flip-flop, comprising:

• an input terminal, configured to receive input data;
• an output terminal, configured to provide output data in response to the input data;
• clock signal terminal(s), configured to receive clock signal(s);
• a first latch unit, configured to latch the input data from the input terminal and transmit the input data under control of the clock signal(s);
• and
• a second latch unit, configured to latch data from the first latch unit and transmit the data latched by the first latch unit under control of the clock signal(s),
• wherein the first latch unit and the second latch unit are sequentially connected in series between the input terminal and the output terminal,
• wherein the second latch unit is a triple gate and an output of the second latch unit is used as the output terminal for driving a load of the dynamic D flip-flop,
• wherein the output of the second latch unit is not connected with an inverter which is used as an output drive unit, and
• wherein the output terminal is configured to provide the output data which is inverted from the input data by directly outputting the data transmitted by the first latch unit and transmitted by the second latch unit, which is not inverted by the first latch unit but is inverted by the second latch unit, as the output data of the dynamic D flip-flop.