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US 12,615,035 B2Granted
Clock synthesizer
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei Shuo Lin, Wei Chih Chen
Life of this patent
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Abstract
A clock synthesizer is provided. A clock buffer is configured to store an input clock signal. A Duty Cycle Corrector (DCC) circuit is connected to the clock buffer. The DCC circuit is configured to receive the input clock signal from the clock buffer, receive a control signal, and adjust a duty cycle of the input clock signal based on the control signal. An output clock signal comprising the duty cycle corrected input clock signal is generated. The output clock signal is provided. A current source is configured to sink a clamping current to the DCC circuit.
Claims20
A clock synthesizer comprising:
- a clock buffer configured to store an input clock signal;
- a Duty Cycle Corrector (DCC) circuit connected to the clock buffer, wherein the DCC circuit is configured to:
- receive the input clock signal from the clock buffer,
- receive a control signal,
- adjust a duty cycle of the input clock signal based on the control signal,
- generate an output clock signal comprising the duty cycle corrected input clock signal, and
- provide the output clock signal, wherein the DCC circuit comprises a duty cycle alterer comprising an input terminal, an output terminal, a first transistor, and a second transistor, wherein the first transistor of the duty cycle alterer is connected between a supply node and a first node of the duty cycle alterer, wherein the second transistor of the duty cycle alterer is connected between the first node and the output terminal of the duty cycle alterer, wherein a gate of the first transistor receives the control signal and a gate of the second transistor receives the input clock signal, wherein an inverted output clock signal is provided at the output terminal of the duty cycle alterer, wherein the DCC circuit further comprises a current source, and wherein the current source is connected to the first node of the duty cycle alterer and is configured to provide a clamping current at the first node of the duty cycle alterer of the DCC circuit.
4 more elements
A method of synthesizing clock, the method comprising:
- receiving, by a duty cycle alterer, an input clock signal, wherein the duty cycle alterer comprises an input terminal, an output terminal, a first transistor, and a second transistor, wherein the first transistor of the duty cycle alterer is connected between a supply node and a first node, wherein the second transistor of the duty cycle alterer is connected between the first node and the output terminal of the duty cycle alterer, and wherein a gate of the second transistor of the duty cycle alterer receives the input clock signal;
- receiving, at a gate of the first transistor of the duty cycle alterer, a control signal;
- adjusting, by the duty cycle alterer, a duty cycle of the input clock signal based on the control signal;
- generating, by the duty cycle alterer, an output clock signal comprising the duty cycle corrected input clock signal, wherein an inverted output clock signal is provided at the output terminal of the duty cycle alterer;
- providing, by a current source connected to the first node of the duty cycle alterer, a clamping current at the first node of the duty cycle alterer;
- and
- providing the output clock signal.
4 more elements
A method of synthesizing clock, the method comprising:
- receiving a clock signal;
- determining, by an error amplifier, a difference between a Direct Current (DC) voltage value of the clock signal and a DC voltage value of an inverted clock signal;
- adjusting, by a duty cycle alterer connected to the error amplifier, a duty cycle of the clock signal based on the determined difference between the DC voltage value of the clock signal and the DC voltage value of the inverted clock signal to substantially equal, wherein the duty cycle alterer comprises an input terminal, an output terminal, a first transistor, and a second transistor, wherein the first transistor of the duty cycle alterer is connected between a supply node and a first node, wherein the second transistor of the duty cycle alterer is connected between the first node and the output terminal of the duty cycle alterer, wherein a gate of the first transistor receives the control signal and a gate of the second transistor receives the clock signal, wherein an inverted output clock signal is provided at the output terminal of the duty cycle alterer, and wherein the duty cycle alterer further comprises a current source connected to the first node of the duty cycle alterer;
- and
- providing, by the current source connected to the first node of the duty cycle alterer, a clamping current at the first node of the duty cycle alterer.
2 more elements
Dependencies are inferred from the claim text.