System and method for memory signal timing calibration with phase control circuit

A device, comprising:

• a semiconductor chip, comprising:
• a memory cell, and
• a memory input-output circuit,
• the memory input-output circuit comprising:
• a first circuit for generating a first data signal;
• a second circuit for generating a second data signal;
• and
• a first phase control circuit,
• the first phase control circuit being configured to perform an operating-mode phase adjustment of a phase of the second data signal,
• the operating-mode phase adjustment being based on whether an edge in an interpolated signal leads or a lags an edge in the first data signal,
• the interpolated signal having a phase between the second data signal and a third data signal.

A method, comprising:

• performing, by a first phase control circuit of a memory input-output circuit, an operating-mode phase adjustment of a phase of a second data signal,
• wherein:
• the memory input-output circuit comprises:
• a first circuit for generating a first data signal;
• a second circuit for generating the second data signal;
• and
• the first phase control circuit;
• the operating-mode phase adjustment is based on whether an edge in an interpolated signal leads or a lags an edge in the first data signal;
• and
• the interpolated signal has a phase between the second data signal and a third data signal.