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US 12,613,815 B2Granted
Fast mass storage access for digital computers
OwnerRobert Gezelterinventor
Life of this patent
Estimating the term…
Abstract
A system for increasing the speed and reducing the time to obtain a required amount of data, from a secondary storage device, for a digital computer, based upon measures to improve the time efficiency of I/O request processing by improving the timing and sequence of transfers to improve the efficiency of mass storage devices.
Claims12
A computing system comprising:
- a CPU;
- random access primary memory (RAM) accessible to the CPU;
- a program executing on the CPU;
- a buffer consisting of consecutive random access primary memory locations directly accessible via CPU instructions;
- a secondary storage device comprising one or more mass storage devices;
- an I/O Interface providing a transfer mechanism between the random access primary memory and the secondary storage device;
- a mass storage transfer request includes direction, (to/from RAM), a starting address in primary memory, a starting mass storage block number, and a block count;
- a controller configured to accept mass storage transfer requests from the I/O interface and control the secondary storage device;
- and
- an operating system configured to initiate data transfers between buffers located in random access primary memory to/from the secondary storage device;
- one or more device drivers that translate program-issued operating system I/O requests into controller requests transferred via the I/O interface to the controller wherein:
- a program invokes an operating system service to enqueue a program request to initiate mass storage transfer requests between program buffers and the secondary mass storage device;
- one or more mass storage devices comprise a sequential mass storage device;
- at least one of the device drivers delays communication of the I/O transfer request until a specified backlog threshold measured in records and/or bytes has been reached;
- the controller receives backlog data bytes and record count from the device driver.
12 more elements
A computing system comprising:
- a CPU;
- random access primary memory (RAM) accessible to the CPU;
- a program executing on the CPU;
- a buffer consisting of consecutive random access primary memory locations directly accessible via CPU instructions;
- a secondary storage device comprising one or more mass storage devices;
- an I/O Interface providing a transfer mechanism between the random access primary memory and the secondary storage device;
- a mass storage transfer request includes direction, (to/from RAM), a starting address in primary memory, a starting mass storage block number, and a block count;
- a controller configured to accept mass storage transfer requests from the I/O interface and control the secondary storage device;
- and
- an operating system configured to initiate data transfers between buffers located in random access primary memory to/from and the secondary storage device;
- the one or more mass storage devices comprise a random access mass storage device wherein:
- a program invokes an operating system service to enqueue a program request to initiate mass storage transfer requests between program buffers and the secondary mass storage device,
- each request for consecutive blocks within a file is expanded into one or more sub-requests for consecutive blocks within a volume with each sub-request containing the corresponding starting buffer address, starting mass storage block number, and length, before any sub-requests are enqueued for processing.
10 more elements
A computing system comprising:
- a CPU;
- random access primary memory (RAM) accessible to the CPU;
- a program executing on the CPU;
- one or more instruction sequences stored in RAM to be executed by the CPU upon request or sub-request completion;
- multiple buffers, each buffer consisting of consecutive random access primary memory locations directly accessible via CPU instructions;
- a secondary storage device comprising one or more mass storage devices;
- and
- an operating system configured to initiate data transfers between buffers located in random access primary memory to/from the secondary storage device wherein:
- the executing program invokes an operating system service once to enqueue multiple independent program I/O sub-requests, with each independent sub-request containing a sub-request-specific completion address of the first instruction of an instruction sequence to be executed by the CPU upon sub-request completion;
- and one or more status return locations.
7 more elements
A computing system comprising:
- a CPU;
- random access primary memory (RAM) accessible to the CPU;
- a program executing on the CPU;
- a secondary storage device comprising one or more mass storage devices;
- a buffer consisting of consecutive random access primary memory locations directly accessible via CPU instructions;
- an I/O Interface providing a transfer mechanism between the random access primary memory and the secondary storage device;
- a mass storage transfer request includes direction, (to/from RAM), a starting address in primary memory, a starting mass storage block number, and a block count;
- a controller configured to accept mass storage transfer requests from the I/O interface and control the secondary storage device;
- an operating system configured to initiate data transfers between buffers located in random access primary memory to/from the secondary storage device;
- and
- one or more device drivers that translate program-issued operating system I/O requests into controller requests transferred via the I/O interface to the controller, wherein:
- a program invokes an operating system service to enqueue a program request to initiate mass storage transfer requests between program buffers and the secondary mass storage device;
- and
- at least one of the device drivers delays communication of the I/O transfer requests until a specified backlog threshold (measured in blocks or requests has been reached) or a time threshold is reached.
11 more elements
A computing system comprising:
- a CPU;
- random access primary memory (RAM) accessible to the CPU;
- a program executing on the CPU;
- a buffer consisting of consecutive random access primary memory locations directly accessible via CPU instructions;
- a secondary storage device comprising one or more mass storage devices;
- and
- one or more device drivers that successively translate program-issued operating system I/O requests into lower-level I/O requests, eventually producing controller requests transferred via the I/O interface to the controller;
- wherein:
- a program invokes an operating system service to enqueue a program request to initiate mass storage transfer requests between program buffers and the secondary mass storage device,
- the operating system or device driver allocates a contiguous composite data structure located in system-owned random access memory containing structure-specific metadata and multiple operating system I/O requests
- where the composite data structure contains active/inactive status of the contained individual operating system I/O requests
- where the composite data structure contains a lock field to coordinate composite data structure access.
9 more elements
Dependencies are inferred from the claim text.