Devices using chiplet based storage architectures

A device for implementing a storage architecture, comprising:

• a front-end chip configured to perform first interfacing with a first device;
• a first back-end package including a package substrate, a first back-end chip configured to perform second interfacing with second devices and disposed over the package substrate, a plurality of memory chips disposed over the package substrate, and a molding structure surrounding the first back-end chip and the plurality of memory chips;
• and
• a second back-end package including a second back-end chip and a second memory chip,
• wherein a first portion of the plurality of memory chips are stacked over a first region of the package substrate and a second portion of the plurality of memory chips are stacked over a second region of the package substrate, wherein a first intermediate substrate is interposed between at least some of the memory chips in the first portion and a second intermediate substrate is interposed between at least some of the memory chips in the second portion,
• wherein the front-end chip includes a first front-end link and a second front-end link for communicating with the first back-end chip and the second back-end chip, respectively,
• wherein the first back-end chip includes a first back-end link in communication with the first front-end link and the second back-end chip includes a second back-end link in communication with the second front-end link,
• wherein the front-end chip is physically separated from the first back-end chip and the second back-end chip to provide the storage architecture having a format different from a system on chip format and a physical separation between the front-end chip and the first back-end chip and the second back-end chip allows 1) the front-end chip to be replaceable separately from the first back-end chip and the second back-end chip while maintaining the first back-end chip and the second back-end chip and 2) the first back-end chip and the second back-end chip to be replaceable separately from the front-end chip while maintaining the front-end chip.