Computer architecture with disaggregated memory and high-bandwidth communication interconnects

A computer system comprising:

• a plurality of memory aggregation devices configured to retrieve data from and store data in a plurality of random access memory modules forming a unified contiguous memory address space disaggregated from a processing unit;
• a plurality of computational devices configured for simultaneously launching a plurality of data signals including memory read and/or write requests for the data to the plurality of memory aggregation devices;
• and
• a plurality of optical links configured for coupling each of the plurality of memory aggregation devices to each of the plurality of computational devices for transferring the data therebetween;
• wherein the plurality of computational devices are configured to read/write multiple read/write requests simultaneously in parallel across the unified contiguous memory address space in the plurality of random access memory modules via the plurality of memory aggregation devices;
• wherein the plurality of optical links comprises a plurality of transmitter optical links and a plurality of receiver optical links;
• and
• wherein the plurality of transmitter optical links comprises:
• a first light source coupled to a first one of the plurality of memory aggregation devices or a first one of the plurality of computational devices configured for generating a first optical beam;
• a first photonic integrated circuit (PIC) mounted on the first one of the plurality of memory aggregation devices or the first one of the plurality of computational devices comprising:
• a first splitter configured for splitting the first optical beam into a plurality of first optical sub-beams;
• a first plurality of modulators configured for modulating the plurality of first optical sub-beams into a plurality of first modulated optical signals;
• a first optical waveguide coupled to an edge of the first PIC configured for transmitting a first one of the plurality of first modulated optical signals from the first one of the plurality of memory aggregation devices or the first one of the plurality of computational devices;
• a second optical waveguide coupled to the edge of the first PIC configured for transmitting a second one of the plurality of first modulated optical signals from the first one of the plurality of memory aggregation devices or the first one of the plurality of computational devices;
• and
• a second photonic integrated circuit (PIC) mounted on the second one of the plurality of memory aggregation devices or the second one of the plurality of computational devices, comprising:
• a first plurality of photodetectors for converting the first one of the plurality of first modulated optical signals and the second one of the plurality of first modulated optical signals into respective electrical signals.