Phase-locked loops (PLL) including digitally controlled oscillator (DCO) gain calibration circuits and related methods

A method of generating an output signal in a phase-locked loop, the method comprising:

• receiving, in a delta detector, a reference clock and a feedback signal;
• generating, in the delta detector, a delta value indicating a time difference between the reference clock and the feedback signal;
• receiving, in a divider circuit, an output clock;
• generating the feedback signal based on the output clock;
• receiving, in an output clock generator, the delta value;
• generating a control signal based on the delta value;
• generating the output clock based on the control signal;
• injecting, by a calibration circuit, a gain correction factor multiplied by a nominal calibration value into the control signal, and
• incrementing the gain correction factor based on the delta value in each of a plurality of cycles of the reference clock until the gain correction factor causes the output clock generator to achieve a nominal gain corresponding to a desired loop bandwidth of the phase-locked loop.

An integrated circuit (IC), comprising:

• logic circuits disposed in a plurality of clock domains, each clock domain comprising a plurality of phase-locked loops (PLLs) configured to generate clocks provided to the logic circuits in a corresponding clock domain, each PLL comprising:
• a delta detector configured to:
• receive a reference clock and a feedback signal;
• and
• generate a delta value indicating a time difference between the reference clock and the feedback signal;
• a divider circuit configured to:
• receive an output clock;
• and
• generate the feedback signal based on the output clock;
• an output clock generator configured to:
• receive the delta value;
• generate a control signal based on the delta value;
• and
• generate the output clock based on the control signal;
• and
• a calibration circuit configured to inject a gain correction factor multiplied by a nominal calibration value into the control signal to the output clock generator,
• wherein the gain correction factor is incremented based on the delta value in each of a plurality of cycles of the reference clock until the gain correction factor causes the output clock generator to achieve a nominal gain corresponding to a desired loop bandwidth of the PLL.