Systems and methods for realizing high-speed low-power wireline transceivers

A method comprising:

• encoding data by:
• receiving a digital data stream that includes a plurality of even and odd numbered bits,
• where the digital data stream has a bit period of one half a symbol period Tsym;
• splitting the digital data stream into a first bit data stream and a second bit data stream, where the first bit data stream and the second bit data stream each has a bit period of one symbol period Tsym, and where each bit in the first bit data stream and the second bit data stream has a voltage value of either zero or one;
• assigning a voltage value of “−1” to each bit in the first bit data stream and the second bit data stream that has a voltage value of zero;
• generating a first periodic clock pulse signal and a second periodic clock pulse signal with alternating values of “−1” and “+1”, each over one symbol period, and where the first periodic clock pulse signal with a period of 2Tsym is orthogonal to the second periodic clock pulse signal with a period of 2Tsym, within a symbol period Tsym;
• multiplying the first bit data stream by the first modulating clock pulse signal creating a first product;
• multiplying the second bit data stream by the second modulating clock pulse signal creating a second product;
• and
• summing the first and second product;
• to create an encoded data stream;
• and
• transmitting the encoded data stream.

An apparatus comprising:

• circuitry configured to create and transmit an encoded data stream, including:
• an encoder including demultiplexer circuitry configured to:
• receive an aggregate transmission of a data stream, the data stream including:
• an integer number M≥2 of same-rate data streams, each data stream in the M same-rate data streams having an ordered number of bits;
• and
• a clock pulse signal including a plurality of pulses where each pulse in the plurality of pulses corresponds to one bit in the aggregated data stream;
• output the M data streams, each data stream in the M data streams having a data rate M times lower than that of the aggregated data stream;
• the encoder further including circuitry configured to generate, using the M data streams output by the demultiplexer, a high speed encoded data stream having
• an ordered number of bits being generated by
• multiplying a data stream in the ordered number M of same-rate data streams by a corresponding clock pulse signal in the ordered number M of orthogonal clock pulse signals to provide M results, and
• summing the M results;
• the encoder further including circuitry configured to transmit the encoded data stream.