Hysteretic comparison circuit

A hysteretic comparison circuit, comprising:

• a comparator configured to receive a first input voltage at a control electrode of a first transistor in a first current branch and a second input voltage at a control electrode of a second transistor in a second current branch, and having an output node configured to provide a single output voltage, the comparator configured to alternately operate in a first phase and a second phase;
• a latch coupled to receive the single output voltage and configured to latch a first indicator which indicates, during the first phase, an under voltage (UV) event when the first input voltage falls below a first threshold voltage and latch a second indicator which indicates, during the second phase, an over voltage (OV) event when the first input voltage exceeds a second threshold voltage, wherein the first and second phases are indicated by a state of the latched first indicator;
• a first current source coupled to a first circuit node of the comparator, the first circuit node located symmetrically between the first and second current branches, and the first current source configured to provide a first bias current to the first circuit node;
• and
• a second current source coupled to a second circuit node of the comparator via a first switch, the second circuit node located asymmetrically between the first and second current branches, and the second current source configured to provide a second bias current, wherein the first switch is selectively enabled by the latched first indicator.