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US 12,609,684 B2Granted
Phase mixer circuit, a phase mixing method, and a clock generation circuit and a semiconductor apparatus
AssigneeSK hynix Inc.
InventorsSoon Chul Kwon, Min Chang Kim, Seul Gi Kim, Hong Joo Song, Ic Su Oh
Life of this patent
Estimating the term…
Abstract
A phase mixer circuit is configured to receive a first input clock signal and a second input clock signal, and to generate an intermediate clock signal having an intermediate phase between phases of the first and second input clock signals. The phase mixer circuit is configured to determine a logic value of a mixed code signal, and to generate an output clock signal by mixing one of the first and second input clock signals and the intermediate clock signal.
Claims21
A phase mixer circuit comprising:
- an intermediate clock generation circuit configured to receive a first input clock signal and a second input clock signal to generate an intermediate clock signal having an intermediate phase between phases of the first input clock signal and the second input clock signal;
- and
- a mixing circuit configured to receive the first input clock signal, second input clock signal, and the intermediate clock signal to generate an output clock signal by mixing the phase of the first input clock signal and the phase of the intermediate clock signal when a target phase of the output clock signal lagging the phase of the first input clock signal is closer to the phase of the first input clock signal than the second input clock signal, and to generate the output clock signal by mixing the phase of the second input clock signal and the phase of the intermediate clock signal when the target phase leading the phase of the second input clock signal is closer to the phase of the second input clock signal than the first input clock signal.
A phase mixing method comprising the steps of:
- receiving a first input clock signal and a second input clock signal;
- generating an intermediate clock signal having an intermediate phase between phases of the first and second input clock signals;
- determining a code value of a mixed code signal;
- and
- generating an output clock signal by mixing the phase of one of the first input clock signal and the second input clock signal and the phase of the intermediate clock signal based on the code value of the mixed code signal.
2 more elements
A phase mixer circuit comprising:
- a phase clock generation circuit configured to receive a first input clock signal and a second input clock signal to generate a first phase clock signal by delaying the first input clock signal, to generate a second phase clock signal by delaying the second input clock signal, and to generate a third phase clock signal having an intermediate phase between phases of the first and second phase clock signals;
- and
- a mixing circuit configured to generate an output clock signal by mixing the phase of the first phase clock signal and the phase of the third phase clock signal when code values of a mixed code signal are first to nth values, to generate the output clock signal by driving the third phase clock signal when the code value of the mixed code signal is an n+1th value, and to generate the output clock signal by mixing the phase of the second phase clock signal and the phase of the third phase clock signal when the code values of the mixed code signal are n+2th to 2n+1th values,
- wherein n is an integer of 2 or more.
1 more element
Dependencies are inferred from the claim text.