Matrix computing method, chip, and related device

A method for computing matrix on a chip, wherein the method comprises:

• buffering, by the chip, a first vector and a second vector, wherein the first vector is buffered in a first buffer, and the second vector is buffered in a second buffer, wherein a plurality of data units in the first buffer are connected to each of K multi-path multiplexers comprised in a first multiplexer of the chip, K is an integer greater than 1, and a connection relationship between an ith multi-path multiplexer in a second multiplexer of the chip comprising K multi-path multiplexers and a data unit in the second buffer is same as a connection relationship between an ith multi-path multiplexer in the first multiplexer and a data unit in the first buffer;
• generating, by a first scheduler of the chip, a first selection signal based on a bitmap of the first vector, wherein the first selection signal causes a first processor to:
• obtain, from the first buffer, a first group of non-zero elements in the first vector, and
• obtain, from the second buffer, a second group of elements in the second vector, and the bitmap of the first vector indicates a non-zero element in the first vector;
• and
• implementing, by the first processor of the chip, an operation between the first vector and the second vector based on the first group of non-zero elements and the second group of elements.