Semiconductor package and method of manufacturing the semiconductor package

A semiconductor package comprising:

• a lower redistribution wiring layer comprising:
• a first chip mounting region;
• a peripheral region provided at a periphery of the first chip mounting region;
• lower redistribution wirings;
• and
• bonding pads electrically connected to the lower redistribution wirings;
• a logic semiconductor chip mounted in the first chip mounting region, the logic semiconductor chip comprising a plurality of first through electrodes that are electrically connected to at least some of the lower redistribution wirings;
• a first sealing member covering the logic semiconductor chip and provided on the lower redistribution wiring layer;
• a plurality of conductive connectors penetrating the first sealing member in the peripheral region, and electrically connected to at least some of the lower redistribution wirings;
• an upper redistribution wiring layer provided on the first sealing member, the upper redistribution wiring layer comprising:
• upper redistribution wirings that are electrically connected to the plurality of conductive connectors;
• a second chip mounting region;
• and
• a third chip mounting region, wherein the second chip mounting region overlaps at least a portion of the first chip mounting region, and the third chip mounting region does not overlap the second chip mounting region when viewed from a plan view;
• at least one memory semiconductor chip provided in the first chip mounting region and the second chip mounting region, the at least one memory semiconductor chip comprises first conductive bumps and second conductive bumps, the first conductive bumps being electrically connected to the plurality of first through electrodes, the second conductive bumps being provided in the peripheral region and electrically connected to the plurality of conductive connectors;
• and
• at least one dummy chip mounted in the third chip mounting region.

A semiconductor package comprising:

• a lower redistribution wiring layer comprising:
• a first chip mounting region;
• and
• a peripheral region provided at a periphery of the first chip mounting region;
• a logic semiconductor chip mounted in the first chip mounting region, the logic semiconductor chip comprising a plurality of through electrodes that are electrically connected to the lower redistribution wiring layer;
• a sealing member covering the logic semiconductor chip and provided on the lower redistribution wiring layer;
• a plurality of conductive connectors penetrating the sealing member in the peripheral region and electrically connected to the lower redistribution wiring layer;
• an upper redistribution wiring layer provided on the sealing member and electrically connected to the plurality of conductive connectors, the upper redistribution wiring layer comprising a second chip mounting region overlapping at least a portion of the first chip mounting region when viewed from a plan view;
• and
• at least one memory semiconductor chip mounted in the second chip mounting region, the at least one memory semiconductor chip comprising first conductive bumps and second conductive bumps,
• wherein the first conductive bumps are provided in the first chip mounting region and the second chip mounting region and are electrically connected to the plurality of through electrodes, and
• wherein the second conductive bumps are provided in the peripheral region and are electrically connected to the plurality of conductive connectors.